decoupling-capacitor
I read many experts here recommend the caps (usually 100nF ones) as close to the power and ground pins as possible. Why do they have to be soldered very near to the pins?
And I used the term decoupling capacitors. Is decoupling and bypass caps same thing in this context.
For these types of packages you should use at least two equal bypass capacitors, one at each side of the IC (one near ground and one near VCC). The parallel inductance of two traces to two different caps lowers the total trace inductance and the current flowing from each bypass cap in opposite directions helps cancel out EMI. See Henry Ott's book "Electromagnetic Compatibility Engineering" for more details here. Apparently this technique reduces noise by a significant amount and will also help functionally. This technique taken to the extreme would involve using a power and ground plane and surrounding the entire chip with bypass capacitors, or if you have the money to spare, using buried capacitance planes, but simply using two caps at either side of the package makes a large and measurable difference (as opposed to just at the VCC side) (I'm too lazy to look it up but I think we're talking 10dB+ improvement).
EDIT: Added my cheesy drawing. The arrows are supposed to show the canceling current loops (one clockwise the other counterclockwise), but note the capacitors should be placed closer to the chip then I drew.
There is a lot here that is difficult to cover. I'll do my best, but be aware that I am leaving things out on purpose. I simply can't cover every issue in the space and time that I have.
You have two main problems: 1. You are basing your electrical design off of old ideas and old rules-of-thumb. 2. You are over thinking things a LOT, especially given the performance of (or lack thereof) your audio amp chip. Let's go over your numbered points:
Another thing to keep in mind is that your amp chip has a typical distortion of 0.1%. This is a lot higher than any improvement you are considering. For example, doing some sort of ground-bounce analysis of your PCB might improve your distortion figure by 0.0001%. But that means that your total distortion might go from 0.1000% to 0.1001%. It just doesn't matter!
Now, let's go to your questions:
You're PCB layout is bad. The main problem is that you are using a "star-ground". Star-grounds are often the wrong thing to use. A PCB like this, where there isn't a lot of noise being generated and everything is fairly close together, a star ground doesn't provide any benefit and often harms things.
Ideally what you want is a 4-layer PCB where one inner layer is a solid ground plane, and the other inner layer is a solid power plane. This provides the absolute lowest power and ground impedance across the entire PCB. (In a moment I'll tell you what to do on a 2 layer PCB.)
What you have are a bunch of individual power/gnd traces that are relatively narrow and will have an impedance that is much higher than a solid plane. Also, the distance between different components is large. For example, the GND path from C3 to U1.3 is three times longer than it should be. Not only will this increase noise, but it increases the loop area. A larger loop area is going to increase your suseptability to external RF noise.
You have similar issues on the power traces. They are relatively narrow and long. This is going to increase the trace impedance and reduce the effectiveness of your decoupling caps.
The correct way to do the PCB layout in 2 layers is to fill the PCB with copper planes. The blue layer would have the GND plane, while the red layer the V+ plane. These planes will be "chopped up" with signal traces, of course, but you will have to carefully route those signals to minimize the negative effects of chopping up the planes.
Best Answer
The ICs contain fast switching transistors generating RF signals. As you know all electrical signals travel in loops. For these ICs the loop is through the power supply pins.
The decoupling caps form a short circuit for these RF signals so the closer you mount the decoupling caps to the power pins of the ICs the smaller the loop will be. This is desirable as it increases the effectiveness of the decoupling because any distance increases parasitic inductance of the wires (about 1 nH per mm). Also large loops emit more RF signals so you have more chance of violating EMI (Electromagnetic Interference) specifications.
Also, a longer distance to the decoupling cap means that the supply voltage inside the IC will be more noisy and polluted with spikes. Worst case the IC stops working because of all the ripple on the supply !
Decoupling caps and bypass caps are indeed the same thing.