Is it because the CPU increases its hertz as necessary?
And when a CPU cycle has to enter a register, does the extra distance in its path measurably affect the speed of that specific cycle? And will it delay the start of the next cycle?
Electronic – Why does the CPU consume more battery during computationally expensive operations
cpu
Related Solutions
See diagrams below to make sense of data flow etc.
- MPC = MicroProgram Counter
- MIR = MicroInstruction Counter
– MPC: Address of next microinstruction to be fetched from memory.
– MIR: Current microinstruction whose bits drive control signals of data path
The question seems to be fundamentally wrong in a statement it makes BUT this may be a language issue - see below.
MIR is NOT loaded FROM MPC (as you say).
MPC is a pointer to the control store and MIR is loaded from the location that MPC points to.
I cannot be 100% sure that I am making sense of your question but if I am then what you suggest is incorrect. You ask -
- " is MIR register loaded from MPC during the control signals are being set up at data path side, or does it happen before?"
If I follow what you are asking then the opposite of what you ask is what happens.
MPC address is latched in by rising system clock
MPC output stabilises during clock high.
MPC now addrses control store so that control store output stabilises by end of system clock less any setup time that MIR may require.
Falling system clock latches control store data into MIR.
Cycle procedes - see below.
SO to the question
- " is MIR register loaded from MPC during the control signals are being set up at data path side, or does it happen before?"
I would answer , No! - MIR register is loaded from the control store (not from MPC) on the falling clock edge AFTER the store output has gone stable which occurs AFTER MPC goes stable which occurs somewhere during clock high.
See below.
BUT following through the following timing should answer it.
Say MIR is loaded by time t1.
(1) Once MIR is loaded the control signals from it propagate asynchronously out onto the data path.
ALU function and data inputs are arranged to be stably set prior to its output being required to be used. This involves two inputs to ALU to be selected by signals from MIR and ALU function also.
(2) Say ALU is stably addressed and data fed and ALU output ready for shifter by t1 + t2.
(3) ALU and shifter then do their thing with output by t1 + t2 + t3.
(4) ALU output is now stored stably back into registers by t1 + t2 + t3 + t4.
This provides next microinstruction address for MPC which outputs control store code for MIR which provides new set of microinstructin bits - cycle repeats.
The above diagram is from page 12 (I think frome here
To the above add the following diagram.
They have used w x y z where I used T1 2 23 4 - you can clearly see the propagation from the cycle triggering clock edge.
The register outputs from the old cycle are loaded on the rising clock edge and MPC is addressed with clock high as the address bots stabilise. MPC becomes valid somewhere in the clock high time. The control store is asynchronously addressed by stabilising MPC and control store output data must be stable by clock fall time (less any setup time required by MIR) so that MIR is loaded from control store on the clock falling edge. The cycle then follows through as above and as per times shown for colours for w x y z below.
The above diagram is slide 6 from here.
Useful references:
THE MICROARCHITECTURE LEVEL
EENG4320 COMPUTER ARCHITECTURE
U of T at Tyler
Here
The Microarchitecture Level
Wolfgang Schreiner
Research Institute for Symbolic Computation (RISC)
Johannes Kepler University, Linz, Austria
here
The Microarchitecture Level - lies between digital logic level and ISA level uses digital circuits to implement machine instructions instruction set can be: implemented directly in hardware (RISC) interpreted by microcode (CISC)
http://www.ics.uci.edu/~bic/courses/51%20ICS/Lectures/ch4-all.pdf
Christmas Tree's Machine
It's a perfectly valid technique, but unless you're sure the signals are glitch-free you need to do a little extra in order to prevent glitches being treated as spurious clocks.
This page describes clock gating with latches, from which I have lifted these diagrams:
The latches should be the "transparent" type.
In general any signal which is an "enable" can be turned into a clock enable if you account for the effects on timing skew.
(I spent about a decade in a startup built around software for automatically managing clock gates and timing in VLSI design!)
Best Answer
There are two effects that influence the amount of power a chip needs. The static power (transistor leakage) and dynamic power. The static power depends on the technology used to build the chip. Therefore even at 0Hz clock the chip draws current. The dynamic power is what you're interested in.
The reason for consuming more power is the number of transistors switching per unit of time. The more transistors switch on or off per second the more power is needed.
Some CPUs indeed throttle their clocks going into different modes. That reduces the number of switches. Others have a capability of turning parts of the CPU off to save energy.
The power heavily depends on which parts of the CPU (die) are used at a given time.