Electronic – Why I can not copy a content of register to another one in “always” block in Verilog

fpgaverilog

well, I have this code, that is working perfectly:

module syncRX(clk, signal, detect);
    input clk, signal;
    output reg [7:0] detect = 0;
    reg [7:0] delay = 0;
    
    //wire clk_1khz;
    freq_div div(.clk(clk), .clk_1khz(clk_1khz));
    
    always @(posedge signal)
     begin
        detect <= detect + 1;
        delay <= 0;
     end
    
    always @(posedge clk_1khz)
     begin
        delay <= delay + 1;
     end
    
endmodule // top

module freq_div(input clk, output reg clk_1khz);
    reg [12:0] count = 0;
    always @(posedge clk)
     begin
        if(count == 6000)
            begin
                clk_1khz <= ~clk_1khz;
                count <= 0;
            end
        else
            count <= count + 1;
     end
    
endmodule

The problem appears when I change the line "detect <= detect + 1;" to "detect <= delay;". The intention is calculate the period of the signal, but I get this warning message of Icestorm: Warning: No clocks found in design

And the FPGA stop working… Please, anyone have an idea what is going bad? Thanks to all!

Best Answer

I think your real problem is that you are trying to load the delay flip-flops on two different edges, signal and clk_1khz. Such a flip-flop is (generally) not synthesizable, so the tools will throw an error if you try to do it. You will need to figure out a way to accomplish your goal without assigning to the same reg in two different always blocks.

Related Solutions

Electronic – Verilog: Break an always block

Yes, you should name your begin-end block and then use disable statement like this:

always @(posedge clk_i or posedge rst_i) begin : block_to_disable
  if(rst_i) begin
    // Do stuff
    disable block_to_disable;
  end

  // Do stuff
end

Though, this is probably non-synthesizable, so you can do such tricks only in simulation (testbenches, etc.).

Electronic – Verilog Adding value in an always block. SIMPLE

always @(*) begin

This means whenever any variable that appears on a right-hand side in the block changes, run the block.

    equals = equals + 1;

This changes the variable equals.

So whenever equals changes, you increment equals. Which means equals changes, which means you increment it again, and so on.

So basically, equals just keeps incrementing as fast as the hardware can make it happen.

If you output this to a 7-segment display, you will just see the superposition of '0', '1', '2', and '3', flashing as quickly as the hardware can go. This will be much faster than your eye can follow. I don't know what it happens to look like, but if you say it looks like a '2', I believe you.

The usual way to do what you seem to want is to make equals increment only when something special happens, like the edge of a slow-ish clock (like maybe 5 Hz at most for the display to be meaningful to the human eye); or only when some special event happens that you're trying to count.

Edit

I should also add that, because of race conditions, if you implement this design in real hardware, it's likely that the output doesn't actually transition through all the states 0, 1, 2, 3, as expected, or that it doesn't do it in the order you expect.

For example if you're in the 2'b01 state, you expect to transition to 2'b10. But the signal to change bit 0 might propagate through more quickly than the signal to change bit 1, resulting in a glitch to the 2'b00 state. If that glitch lasts long enough, the circuit might go from there to the 2'b01 state again instead of to 2'b10. But that's just an example. What really happens depends on the transistor-level and wire-geometry level details of how the circuit is built.

Best Answer

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Electronic – Verilog: Break an always block

Electronic – Verilog Adding value in an always block. SIMPLE

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