Electrical – Sending a divided clock through a non-dedicated clock pin

artix-series-fpgaclockerrorfpgaperipheral

I'm moderately new to FPGA's, and right now I'm working on code to interface with a DAC. I'm using this PMOD DAC , and a Nexys 4 DDR fpga. Right now, I'm connecting them through the JB PMOD header.

The DAC requires a clock pulse (I'm sending in a 50MHz one, which I've divided from the FPGAs 100MHz clk), which I'm sending in through pin 4, following the reference manual. However, once I try to synthesize and implement it, I get an error.

"Poor placement for routing between an IO pin and BUFG. If this sub-optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .XDC file to demote this message to a warning. However, the use of this override is highly discouraged. These examples can be used directly in the .XDC file to override this clock rule.
"

There are two possible problems:

The fpga doesn't like that I'm outputting a clock signal through this PMOD pin
There may be an issue with Mset_enable, but it has nothing to do with a clock (right now it's an input assigned to one of the on-board buttons), and I see no reason why there should be difficulty placing it.

My question is: which problem is it, and should I go ahead and use this workaround?

Mset code:

module tuning_word_set(
  input [3:0]data_in,
  input clk,
  input Mset_enable,
  output reg sin_LUT_rst,
  output reg [3:0]data_out
  );

//if enabled, M will change to data_in, otherwise it will stay the same
always @*
begin
  if (Mset_enable)
  begin
    data_out <= data_in;
    sin_LUT_rst <= 1'b1;
  end
  else
    data_out <= data_out;
    sin_LUT_rst <= 1'b0;
end

endmodule

Best Answer

What you can try, rather than dividing the clock, is just creating a 50 MHz clock in the constraints file, and tying that the output pin.

This will get you started on the right track: http://www.xilinx.com/support/answers/62488.html

Related Solutions

Synchronizing input and output

I think I'd have answered this interview question the same way you did. I believe the interviewer's requirement "to be done without a FIFO" was because a FIFO buffer is a valid, practical way to solve the problem of multiple clock domains -- but it can be done without the head/tail logic of a complete FIFO in many cases. And in the context of a job interview, simply instantiating a standard module doesn't demonstrate that you understand how to approach FPGA / HDL design. (I've interviewed candidates who couldn't even manage that small task.)

Passing data between different clock domains is usually done with three stages of flip-flops. The first stage is in the source clock domain (clkA), and the second and third stage flip-flops are in the receiver clock domain (clkB). The setup time of the second stage flip-flop is sometimes violated because the clocks are not synchronous, so the third-stage flip-flop is used to clean up the timing. Since there is a delay, the data_valid signal is passed in parallel with the data.

module SyncExample (
    input   wire            clkA,
    input   wire    [7:0]   Data_in,        // in clkA clock domain
    input   wire            Data_valid,     // in clkA clock domain
    input   wire            clkB,
    output  reg     [7:0]   Data_out,       // in clkB clock domain
    output  reg             Data_out_valid  // in clkB clock domain
    )

// First stage pipeline registers the clkA clock domain signals.
// pipeline_1_valid is set by Data_valid and remains set 
// until cleared by pipeline_1_valid_clear acknowledge from clkB domain.
reg [7:0] pipeline_1_data;
reg       pipeline_1_valid;
wire      pipeline_1_valid_clear;
initial begin
    pipeline_1_data <= 0;
    pipeline_1_valid <= 0;
end
always @(posedge clkA) begin
    if (Data_valid) begin
        // capture pipeline_1_data only when Data_in is valid
        pipeline_1_data <= Data_in;
    end
    // keep pipeline_1_valid set after Data_valid, until pipeline_1_valid_clear.
    pipeline_1_valid <= (Data_valid | (pipeline_1_valid & ~pipeline_1_valid_clear));
end

// Second stage pipeline registers the clkB clock domain signals.
// Because clkA and clkB are asynchronous clock domains, 
// setup time cannot be guaranteed for this stage.
// The previous pipeline_1 stage holds its data valid for
// more than one clkA cycle, to help achieve clkB setup requirement.
reg [7:0] pipeline_2_data;
reg       pipeline_2_valid;
initial begin
    pipeline_2_data <= 0;
    pipeline_2_valid <= 0;
end
always @(posedge clkB) begin
    pipeline_2_data <= pipeline_1_data;
    pipeline_2_valid <= pipeline_1_valid;
end

// Third stage pipeline registers the clkB clock domain signals.
initial begin
    Data_out <= 0;
    Data_out_valid <= 0;
end
always @(posedge clkB) begin
    Data_out <= pipeline_2_data;
    Data_out_valid <= pipeline_2_valid;
end

// pipeline_1_valid_clear timing feedback signals when the data-valid signal
// has propagated through all stages.
// For this simple example, we assume data_out is captured as soon as it is valid.
// A practical application should instead drive this with a read_data_out command.
assign pipeline_1_valid_clear = Data_out_valid;

endmodule;

You can also find similar example code in Xilinx ISE Language Templates under Verilog | Synthesis Constructs | Coding Examples | Misc | Asynchronous Input Synchronization.

edit: Added pipeline_1_valid_clear signal and set/clear behavior to meet the slower clock domain's minimum pulse width requirement. Capture pipeline_1_data only when Data_in is valid.

Electronic – How to solve routing issues in Artix7

It's recommened to use clock capable pins (CC Pins) for clock inputs. These can be routed to BUFGs.

But the error it in another part of your code. As you wrote you are using

if rising_edge(input) then

You cannot use rising_edge on none clock nets, this promotes them to a clock net, which input isn't.

The correct way is to synchronize the input with 2 D-FF and add an edge detection after that (3rd D-FF, not-gate, and-gate). All FF are driven by your system clock.

input_meta <= input      when rising_edge(Clock);  -- 1st synchronizer D-FF
input_sync <= input_meta when rising_edge(Clock);  -- 2nd synchronizer D-FF
input_d    <= input_sync when rising_edge(Clock);  -- edge detection D-FF (d = delayed)
input_re   <= not input_d and input_sync;          -- edge detection equation (re = rising edge)

process(Clock)
begin
  if rising_edge(Clock) then
    if (input_re = '1') then
      -- do something
    end if;
  end if;
end process;

Best Answer

Related Solutions

Synchronizing input and output

Electronic – How to solve routing issues in Artix7

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