Electronic – How to solve routing issues in Artix7

artix-series-fpgavhdlvivadoxilinx

I am working with Artix 7 (xc7a15tftg256). When the time of Run Implementation,shows the following error message:

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets input_IBUF] >

  • input_IBUF_inst (IBUF.O) is locked to IOB_X0Y83
  • input_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y30

For my application I check rising_edge(input). Kindly provide the solution in this problem.

Best Answer

It's recommened to use clock capable pins (CC Pins) for clock inputs. These can be routed to BUFGs.

But the error it in another part of your code. As you wrote you are using

if rising_edge(input) then

You cannot use rising_edge on none clock nets, this promotes them to a clock net, which input isn't.

The correct way is to synchronize the input with 2 D-FF and add an edge detection after that (3rd D-FF, not-gate, and-gate). All FF are driven by your system clock.

input_meta <= input      when rising_edge(Clock);  -- 1st synchronizer D-FF
input_sync <= input_meta when rising_edge(Clock);  -- 2nd synchronizer D-FF
input_d    <= input_sync when rising_edge(Clock);  -- edge detection D-FF (d = delayed)
input_re   <= not input_d and input_sync;          -- edge detection equation (re = rising edge)

process(Clock)
begin
  if rising_edge(Clock) then
    if (input_re = '1') then
      -- do something
    end if;
  end if;
end process;
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