PlanAhead 14.7 multiple runs issues

planaheadspartan 6vhdlxilinx

My project in PAhead 14.7 have 6 different synthesis run and 6 implementation runs. Each implementation run have her own parent synthesis run. The differences between synthesis runs are some generic parameters to customize each synthesis to a country. These custom generics have been introduced in the "More options" parameter of each synthesis, for example -generics {g_COUNTRY="CANADA"} -shreg_min_size 6

In order to synthesize and implement quickly taking advantage of modern multicore processors I have wrote a tcl script that:

  1. Reset outdated implementation and synthesis runs
  2. Launch outdated synthesis runs
  3. Wait for completion of synthesis runs
  4. Launch outdated implementation runs
  5. Wait for completion of implementation runs
  6. And finally generate the bitstream file

Here some main parts of the launching runs tcl code

# Launch all the synthesis runs with a maximum of $jobQuantity jobs
launch_runs $synthRuns -jobs $jobQuantity
# Wait for completion of all runs
foreach synthR $synthRuns {wait_on_run $synthR}

# Launch all the implementation runs with a maximum of $jobQuantity jobs
launch_runs $implRuns -jobs $jobQuantity
# Wait for completion of all runs
foreach implR $implRuns {wait_on_run $implR}

The big problem is that when all the runs have finished, in the GUI I found inconsistent results. For example, when I open each synthesized run in PAhead GUI to verify her customization, always is opened the results of the active synthesis run the tcl script was executed.

  • Each synthesis report file has been verified and is correct.
  • Each ngc result file in each synth directory has been verified and is correct.

But PlaheadGUI always open the active synthesis run during the launch command, even when changed the synthesis active run to other.

And worst. When launching the implementation runs, all the implementation runs have taken as synthesis parent the active synthesis run. So all the implementation runs have the same and incorrect results. These same wrong results have been verified in FPGA Editor for each implementation run.

The TCL script have been executed in GUI mode and interactive mode with the same wrong results

What's going on? PlanAhead 14.7 is not capable of manage multiple runs? Any setting could be wrong?

Best Answer

Unfortunately PlanAhead do not manage correctly the simultaneous launch of multiple runs.

I recommend use only one synthesis and one implementation runs. Nevertheless, I haven't test if results are right setting multiple runs and launch them sequentially.