Inferring D-latch on Zedboard within Vivado Error

fpgavhdlvivado

I'm trying to implement a simple latch on a ZedBoard via Vivado. 

begin
process(D,Enable) begin
   if(Enable = '1') then 
       Q <= D;
       Qbar <= not(D);
   end if;
end process;

I'm using user I/O on the constraints for the inputs/outputs. I assign the inpus to two SWITCH Pins and the outputs to two LED pins.

The routing (implementation phase) gives me the following error:

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Enable_IBUF] >

Enable_IBUF_inst (IBUF.O) is locked to IOB_X1Y125
and Enable_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31`

The two suggested solutions to the problem are here and setting the < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Enable_IBUF] > works but I would like to understand solution 1
1) Move the clock input to a clock capable pin. since it seems important.

How can I find a clock capable input that I can press/move like I do on the switch?

Edit: Link of the ZedBoard pins (already tried C19 -> FMC_CLK1)

Best Answer

What's happening here is that the tools are interpreting your Enable signal as a clock. (You can view your implemented design in the tool to check this.) If you attempt to design some asynchronous logic, the tools generally try very hard to find a clock, because FPGA timing models assume a synchronous system.

So you are getting the CLOCK_DEDICATED_ROUTE warning because the tools think the enable signal is a real clock. If it was a real clock, you would want to use the special clock pins on the FPGA that are directly connected to clock routing resources. (These are labelled MRCC and SRCC, for multi-region and single region, respectively.) But since your signals are coming from physical switches, for the purposes of your experiment the non-ideal routing doesn't really matter.

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