I have read on several places that NOR flash have lower latency when it comes to reading compared to NAND version but I don't understand is this architectural consequence or due to, often different, interfaces.
Electronic – Why is NAND flash slower than NOR when it comes to reading
flashnand-flash
Related Solutions
It looks like you can get the datasheet for the flash chip and thereby rig up something to read the bits. However, that may be a long way from recovering the data. Somewhere in the pile of bits is control information private to the flash drive, probably some wear levelling data, and then file system structures as seen by the operating system.
You should be able to get info on the file system (probably FAT32), but the private flash drive structures and how/where it actually stores the data is unlikely to be specified publicly. I think the best bet is to get another flash drive of the exactly the same model, replace your flash chip into that drive, and hope no additional state is stored in non-volatile memory in the controller.
Short answer:
You are using OpenOCD in LE mode when your CPU runs on BE (or vice-versa).
You have to specify the correct -endian switch for the target command in your OpenOCD configuration.
Longer asnwer:
Where is the endianness mismatch?
Regardless of endianness, the data is being read from the flash one chip_bus_width bits at a time, in this case 16bits. The order and width (apparently 32) in which the nibbles are sent serially over the JTAG bus depends on the CPU endianness and OpenOCD has no way (without interference) to guess this if the particular CPU can run in either mode (like MIPS or ARM cores can).
It is the CPU itself that is performing the actual read operation, commanded by the TAP controller. This would not be the case if poking the flash using boundary scan.
For both mdw or dump_image OpenOCD commands, your 4 bytes will be reversed if your OpenOCD has a mismatching endianness (-endian) setting.
Endianness and byte sequences, or strings
As stated in some comments, C strings and byte arrays will always appear in-order when inspecting the memory in 1 by 1 increments, and thus should appear in-order if we dumped that memory into a file. That is part of the ANSI C standard, and set in stone by how pointer arithmetic works:
When an expression that has integral type is added to or subtracted from a pointer, the result has the type of the pointer operand. If the pointer operand points to an element of an array object, and the array is large enough, the result points to an element offset from the original element such that the difference of the subscripts of the resulting and original array elements equals the integral expression.
Increasing the address by one we always get the next-in-sequence byte (or char in a string), regardless of the endianness. It cannot be said more clear: Endianness does NOT affect how C-Style strings are stored.
Hex dump at address 0x000000e0 of a printf("Hello, world!");:
C object code, compiled for big endian (mips-gcc -EB):
48 65 6c 6c 6f 2c 20 77 6f 72 6c 64 21 00 00 00 |Hello, world!...|
C object code, compiled for little endian (mips-gcc -EL):
48 65 6c 6c 6f 2c 20 77 6f 72 6c 64 21 00 00 00 |Hello, world!...|
Integers (and bigger numbers) in the other hand, are stored in the byte order of the particular endianness, and examining an integer number in RAM or in the flash (or in a dump file, etc.) byte by byte, will yield different sequences for BE or LE, very loosely related with the actual issue.
Best Answer
The difference in read speeds between NOR (few nanoseconds) and NAND (microseconds) is due to the difference in architecture of read logic. just consider the read operation of just one bit (the arrangement of bit and word lines in NOR vs. NAND is a different topic). The read of each memory cell is done by applying convenient voltages to its terminals and measuring the current that flows into the cell. NOR and NAND memories measure this current in different ways:
NOR:
The read operation is done differentially. The desired cell is biased and at the same time a 'reference cell' is biased with the same voltage. the current in both is measured and then compared. The biasing (both measuring and reference cell), equalizing, and current comparison takes around nanoseconds in modern flash memories.
NAND
In NAND the cells are connected in series and therefore the current to be read/sense is 200–300 nA. This makes the differential sense method difficult; instead, charge integration is used. The bitline is charged by a defined amount and then checked whether it gets discharged (indicating that bit is erased) or not (no discharge means the cell/bit is not sinking and therefore set). The setup time to precharge the bitline (2-6 µs), then to let it discharge and evaluation (5-10 µs), is what takes time and makes the NAND read operation slow.