Commonly, the best practice 4-layer PCB stack up is (from top to bottom) signal-ground-power-signal. That keeps the signal layers close to a reference plane, and allows signals to be routed directly to the components.
Alternatively, for stringent EMC requirements, power-signal-signal-ground can be used to provide some shielding at the expense of ease of re-work and component-signal routing.
Other more exotic stack-ups can be used with care.
Why then, is signal-power-signal-ground not generally recommended? It maintains the signals-close-to-reference-plane characteristic while adding a shielded signal layer for those signal worth shielding. For slower/less critical signals, the top signal layer provides convenient routing. Additionally the bottom ground layer potentially provides better heatsinking options.
The only concern I've come across is that the asymmetry can lead to warping during manufacture.
Why is this stack-up generally not recommended, and what is the mechanism of the warping issue?
Best Answer
If SMT components are mounted on both sides, you would rip up the outer power/ground plane in a S-P-S-P (Signal - power/gnd Plane - Signal - power/gnd Plane) stack up in order to place solder pads and place traces between these pads and vias.
In order to reach or to leave the signal plane that is sandwitched between power/ground planes, you **have to* use via's. This will detoriate the return path.
Alhough this problem can also exist with a S-P-P-S stack up, you may find ways to avoid using vias by routing the signals subjected to this issue first.