Alright. I was given the task to design an analog design board which contains lots of opamps, some CMOS switches and some ADCs/DACs. It also contains 4 separate power supplies (each supplying +5V and -5V (+5VA1 .. +5VA4, -5VA1 .. -5VA4, AGND1..AGND)) plus some 3V3/ DGND logic.
Space was an issue so I was limited regarding placement and routing. I decided on 8 layers, wheras 4 of them are power planes (all of them are split planes). I designed them like this:
- Top Layer (Signals in all directions, components)
- MidLayer1 (Signals in horizontal direction)
- MidLayer2 (Signals in vertical direction)
- Power Plane 1 (AGND Plane): AGND1..AGND4
- Power Plane 2 (POSitive Plane): +5V (digital!), +5VA1..+5VA4
- Power Plane 3 (NEGative Plane): -5VA1..-5VA4, +3V3
- Power Plane 4 (DGND Plane): DGND (required in large areas)
- Bottom Layer (Signals in all directions, components)
Now I wanted to know what would be the "optimum" layer stackup. Signals are not high speed, just some rather low speed analog, relatively precise signals. Often, signals will pass from Top to Bottom (this was required because of the limited space), yet usually signals between OPamps will stay on either top or bottom layer.
Top and Bottom are given, now I was wondering if I should embed the middle layers within power pairs, or if I should put both GND planes into the middle.
Any ideas on this? There is some digital logic on the board as well, but it's mostly low speed communication.
Best Answer
The main consideration is that any high speed or sensitive analog tracks should run over an unbroken reference plane. This could be a power plane or a ground plane, but these sensitive tracks shouldn't run over a split in the plane.
Without knowing more about your design I can't say whether you have enough ground planes or if you need to figure out how to use fewer split planes and more ground planes or if you even need to use a 10 layer stack-up.