Electronic – Why use a tantalum instead of a ceramic capacitor

ceramic should work as long as you meet the requirements in the datasheet: 0.1ohm < esr < 5ohm and srf > 1mhz.

Its probably easier to find those properties in a tantalum cap, especially back in 2002 when that datasheet was released.

EDIT: Some more info about LDO stability and why the ESR has to fall in a particular range.

A generic LDO works by comparing the output voltage to an internal voltage reference with an error amplifier and driving a PNP transistor to correct for this error.

The problem comes in when you look at the phase shift and loop gain of this feedback path. The error amplifier and the load being driven both contribute poles to the frequency response of the feedback loop. These poles act as a low pass filter resulting in loop gain decreasing as frequency increases. As we know a pole also introduces a negative phase shift. If this phase shift is allowed to reach -180deg the feedback loop becomes unstable and the LDO will oscillate.

What this means is that every time the error amp tries to compensate for an error the result of its correction is 180deg out of phase, or inverted, consequently the error amp is basically thrown for a loop and begins making the opposite correction that it should be making, resulting in wild instability.

To avoid this situation we need to prevent the phase shift in the feedback loop from ever getting to -180deg, actually we only need to keep it from reaching -180deg within the region that the LDO can generate gain > 1 as the damped response of the system past this point will prevent oscillation. This frequency is defined by the unity-gain point of PNP pass transistor.

The way we prevent this phase shift is by using a capacitor with a ESR in a certain region. The capacitance will shift the pole created by the load but more importantly the ESR will contribute a higher frequency zero. Basically you've added a high pass filter to the feedback loop. The phase shift introduced by the ESR will work to counteract the phase shift introduced at lower frequencies by the poles from the error amp and the load.

The reason that the ESR has to be in a particular range is that if its too low, the zero contributed to the frequency response will be located very high in frequency, above the unity-gain point of the pass transistor. As a result its not effective in making sure the phase shift of the feedback loop doesn't reach -180deg before the unity-gain frequency.

If the ESR is too high, the zero will be very low in frequency. There is another pole in the frequency response created by the parasitics of the pass transistor, if the zero from the capacitor ESR is too low in frequency, this pole will be reached while we still have gain > 1, this will cancel out the effect of the ESR zero and we will likely reach -180deg phase shift before we reach unity gain.

All that said, these problems are indicative of older LDO designs. Many/Most/All new designs include additional internal compensation in the feedback loop which uncouples LDO stability from the ESR specification of the output capacitors.

You can replace the aluminum electrolytic with a tantalum, but using neither is a much better choice.

Nowadays, ceramics can easily cover the 10 µF at 10s of volts range. There is no point using either a electrolytic or tantalum. You also don't need a separate 100 nF (that value is so 1980s anyway) capacitor if you use a ceramic for the larger value.

Think about what is going on here and what the datasheet is trying to say. These devices are notorious for being quite sensitive to power supply noise. I've actually seen a similar part amplify power ripple from the power supply to the output. The datasheet therefore wants you to put a "large" amount of capacitance on the power line to the device. That's where the 10 µF came from. Back when this datasheet was written, or whoever wrote it stopped keeping up with developments, 10 µF was a unreasonably large request for any capacitor technology that was good at high frequencies. So they suggest a electrolytic for the 10 µF "bulk" capacitance, but to then place a 100 nF ceramic across that. That ceramic will have lower impedance at high frequencies than the electrolytic, despite the fact that it has 100 time less capacitance.

Even in the last 15-20 years or so, that 100 nF could have been 1 µF without being burdensome. The common value of 100 nF comes from the ancient thru-hole days. That was the largest size cheap ceramic capacitor that still worked like a capacitor at the high frequencies required by digital chips. Look at computer boards from the 1970s and you will see a 100 nF disk capacitor next to every one of the digital ICs.

Unfortunately, using 100 nF for high frequency bypass has become a legend on its own. However, the 1 µF multi-layer ceramic capacitors of today are cheap and actually have better characteristics than the old leaded 100 nF caps of the Pleistocene. Take a look at a impedance versus frequency graph of a family of ceramic caps, and you'll see the 1 µF has lower impedance just about everywhere compared to the 100 nF. There may be a small dip in the 100 nF near its resonant point where it has lower impedance than the 1 µF, but that will be small and not very relevant.

So, the answer to your question is to use a single 10 µF ceramic. Make sure whatever you use still is actually 10 µF or more at the power voltage you are using. Some types of ceramics go down in capacitance with applied voltage. Actually today you can use a 15 or 20 µF ceramic and have better characteristics across the board compared to the 100 nF ceramic and 10 µF electrolytic recommended by the datasheet.