Electronic – Will DDR2 memory work with DM pins tied to LOW, if no data masking is required

It depends on the particular processor whether "registers" are in the same address space as regular data memory or separate. In either case, if there are multiple of them each one still needs a address.

Let's say the processor has 16 registers that are tightly coupled to the CPU and implemented separately from data memory. Those registers still have to be identified somehow. In this case, a 4 bit address would be needed to distinguish individual registers. In a RISC architecture, the 4-bit address of whatever register(s) a instruction worked on would be included in the instruction code. For example, the ADD instruction might add the value of a source register into a destination register. That instruction would include 4 bits to identify the source register and another 4 bits to identify the destination register. The documentation may refer to these registers by "number" 0 to 15, but that's really the address of where the registers lives in a special small memory by the CPU.

In addition to the above, even when a processor has special dedicated registers, those registers might be mapped into the general purpose data address space. References to those addresses are trapped and referred to the internal registers.

There are lots of schemes out there, but if you have more than one register, those registers need to be distinguished from each other somehow, and inside the hardware that will be with a "address", whether it is called that in the documentation or not.

I think you have it right. There are 16k bits, which is 2k bytes.