I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution but I think that the solution is wrong.
Consider an instruction pipeline with five stages without any branch
prediction: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch
(OF), Execute (EX) and Operand Write (OW). The stage delays for IF, ID,
OF, EX and OW are 5 nsec, 7 nsec, 10 nsec, 8 nsec and 6 nsec, respectively.
There are intermediate storage buffers after each stage and the delay of
each buffer is 1 nsec. A program consisting of 12 instructions I1, I2, …, I12
is executed in the pipelined processor. Instruction I4 is the only branch
instruction and its branch target is I9. If the branch is taken during the
execution of this program, the time needed to complete the program is:
a. 132 nsec
b. 154 nsec
c. 176 nsec
d. 328 nsec
Correct answer is (b).
Minimum clock period = max{5,7,10,8,6} + 1 = 11
I1: IF ID EX ME WB
I2: IF ID EX ME WB
I3: IF ID EX ME WB
I4: IF ID EX ME WB
I5: . . . . .
I6: . . . . .
I7: . . . . .
I8: . . . . .
I9: IF ID EX ME WB
I10: IF ID EX ME WB
I11: IF ID EX ME WB
I12: IF ID EX ME WB
Total 14 clock cycles are needed, i.e. 14 x 11 = 154 nsec
The solution was provided along with the question but I think it is wrong. In the solution the IF stage of I9 was executed at ME stage of I4 but I think it should execute with WB stage of I4.
Can someone please help me?
References:
Week 11: Assignment Solutions Question number 2.
Please refer here if the solution is not clear.
Best Answer
The reference solution to the exercise is inconsistent: The exercise states that the five stages are "IF, ID, OF, EX, WB" but the solution then assumes a different pipeline consisting of "IF, ID, EX, MEM, WB", effectively shifting the Execute operation to an earlier location in the pipeline and thereby making the branch take one less clock cycle. In any case, the actual jump happens during the Execute stage; that is, once the EX stage of the branch has completed, the next instruction will be fetched from the jumped-to location.
Given the original five pipeline stages stated in the exercise (IF, ID, OF, EX, WB), the instruction sequence will in fact need 15 clock cycles to execute.