Electronic – Xilinx ZYNQ/ARTIX7 Invert Clock without inducing skew

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For HDL design I'm currently developing for a zynq SoC, I need to invert a clock signal because of a swapped differential pair on board level.

Using "NOT" to invert adds a LUT in the path and as such introduces skew of at least 500ps between the inverted one and the original one (which is also put on an other differential output. And this is too much in our case.

Is there a way to invert a clock signal so that the skew between the original and the inverted copy is minimal?

I have found a possible solution using the ODDR primitive but this seems more like a workaround than a solution.

Thanks in advance.

Best Answer

With Xilinx devices, using an ODDR is actually the recommended way to output a clock signal on a pin, especially if you have tight timing constraints. Do this for both clk and clk180, and both will have the same, repeatable timing. It is not a workaround at all.

See comment on the Xilinx forum here by a Xilinx Engineer:

ODDR keeps the duty cycle and provides the best possible path. No routing of clock on any interconnect, clock remains on the global clock resources where they belong.

It's also mentioned in the Xilinx 7-Series Select IO user guide, page 128, section "OLOGIC Resources" > "Clock Forwarding":

Output DDR can forward a copy of the clock to the output. This is useful for propagating a clock and DDR data with identical delays, and for multiple clock generation

You could play around with balancing LUT delays with other LUTs, ODELAY, and constraints, but this will not approach the simplicity or timing predictability of the ODDR method.

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