Wiki says...
In a depletion-mode MOSFET, the device is normally ON at zero gate–source voltage. Such devices are used as load "resistors" in logic circuits (in depletion-load NMOS logic, for example). For N-type depletion-load devices, the threshold voltage might be about –3 V, so it could be turned off by pulling the gate 3 V negative (the drain, by comparison, is more positive than the source in NMOS). In PMOS, the polarities are reversed.
So for a depletion-mode PMOS it is normally ON at Zero volts but you need 3V or more on the gate higher than the supply voltage to turn OFF. Where do you get that voltage? I think , that's why it is uncommon.
In practise now we call them High Side Switches or Low Side switches for power MOSFETs. They prefer not to combine enhancement and depletion mode in the same chip as the processing costs are almost double. This patent defines some innovation and better physical desc. than I can remember. http://www.google.com/patents/US20100044796
It is possible though what you are suggesting and performance are key issues. However when it comes down to low ESR, MOSFETS are like voltage controlled switches with ESR changing over a wide range of DC voltages unlike bipolar transistors which are 0.6 to < 2V for max peak in some case. Also for MOSFETs it is constructive to think of them as having an impedance gain of 50 to 100 when looking at loads and ESR of source. So consider you need a 100 ohm source to drive 1 ohm MOSFET and 10 ohm source to drive a 10mΩ MOSFET if you use 100:1, Conservative is 50:1. This is ONLY important during the transition period of the switch, not the steady state gate current.
Whereas bipolar hFE drops dramatically so you consider hFe of 10 to 20 good when saturated for a power switch.
Also consider that MOSFETS as charge-controlled switches during transition, so you want to have a big charge available to drive the gate capacitance and load reflected into gate with a low ESR gate drive, if you to make a fast transition and avoid commutation ringing or bridge cross-over shorts. But that depends on design needs.
Hope that isn't too much info and the patent explains how it works for all modes of P N type depletion and enhancement in terms of device physics.
When you apply a voltage to the gate of an NMOS FET that is greater than the threshold voltage \$V_{t}\$, a channel of electrons is formed under the gate. That channel connects the drain and source so that when you apply a voltage \$ V_{ds}\$, a current flows from between these terminals. In this mode, the MOSFET behaves almost like a resistor, so the current flow depends (although not linearly) on \$V_{ds}\$, but the current will also increase with the gate-source voltage \$V_{gs}\$ because increasing this makes the channel deeper, reducing its resistance. That explains the first part of the curve (active or triode).
However, the electric field near the drain depends not just on \$V_{gs}\$ but also on \$V_{ds}\$. Once \$V_{ds} = V_{gs} - V_{t}\$ (called \$V_{ds,sat}\$) the electric field is cancelled near drain and the channel becomes shorter, no longer reaching the drain, leaving a depletion region between the end of the channel and the drain. Any further increase in \$V_{ds}\$ is dropped across this depletion region so the voltage across the channel stays constant at \$V_{ds,sat}\$ and the current flow is also constant. That is the second region of the curve (saturation).
The explanation of the saturation region above would suggest that FET current is constant with \$V_{ds}\$ in the saturation region. Obviously, from the current-voltage curves we can see that this is not the case, and actually the current slowly rises. This is due to an effect called channel length modulation. As \$V_{ds}\$ continues to increase, it cancels the inverted channel even further from the drain, leading to the channel shortening. This reduces the channel resistance (resistance is proportional to length) leading to higher current flow.
There are obviously a lot of second order effects not covered here, but those are the basics!
Best Answer
Your Channel is Itself in depletion region
To understand whats happening imagine a freshly created MOSFET a just newly put together wafer(
though they are diffused with impurity but just for example lets imageine),so as you are using NMOS your substrate is P type,and Source and Drain is N type.At first instant both the regions of the Source and Drain they have both carriers(e in S and D and holes in P substrate) which will diffuse across the barrier creating a depletion region i.e there are no charge ,only immobile ions there,the diffusion will stop when a voltage cause by the immobile ions exceed the gradient voltage of carriers.
This voltage now stops the diffusion of the carriers,and is called the Threshold Voltage.(Vth)
Now as your NMOS is enhancement type you will have no pre-made channel,all you have is depletion region lying between the DRAIN and the SOURCE.A channel is one which has free carrier to casue flow of charge,you already have a depletion region all you need is charge.
Voltage through gate that will be act against the Threshold voltage,and hence will create a voltage difference along with action of attracting electrons form the substrate to act as carrier in depletion region.Now By applying a suitable Drain voltage you can have a current flow through the channel.