Error Loading Design Unresolved Reference

verificationverilog

Please help!

DUT: AND gate

module ANDgate(a, b, c);
input a;
input b;
output c;
assign c = a & b;
endmodule

TESTBENCH: Without task

`include "simple_task.v"    
module task_calling();
  reg tb_a;
  reg tb_b;
  wire tb_c;  

ANDgate myAND (
  .a(tb_a),
  .b(tb_b),
  .c(tb_c));

always
  begin 
    task_ANDinputs(tb_a, tb_b);
    $display ("time = ", $time, " a = %d, b=%d, c=%d", tb_a, tb_b, tb_c);
  end  

endmodule

TASK:

`include "ANDgate.v"
module simple_task();

task task_ANDinputs(output x, output y);

begin
  x = 1'b1;
  y = 1'b0;
end

endtask

endmodule

Question, there is no compilation error, but it says ERROR LOADING DESIGN. Is there a problem with my program? The only use of the task is to input 1 and 0 to x and y respectively. And this is the detailed errror: ** Error: (vsim-3043) C:/altera/14.1/Simple Task 2/task_calling.v(14): Unresolved reference to 'task_ANDinputs'.

Please advise.

Best Answer

You must not include another module within the module/endmodule keywords. I no longer get errors when I make the following changes:

task_calling.v:

`include "ANDgate.v"

module task_calling();

`include "simple_task.v"
  reg tb_a;
  reg tb_b;
  wire tb_c;  

ANDgate myAND (
  .a(tb_a),
  .b(tb_b),
  .c(tb_c));

initial
  begin 
    task_ANDinputs(tb_a, tb_b);
    $display ("time = ", $time, " a = %d, b=%d, c=%d", tb_a, tb_b, tb_c);
  end  

endmodule

simple_task.v:

task task_ANDinputs(output x, output y);

begin
  x = 1'b1;
  y = 1'b0;
end

endtask

I changed your always to an initial to avoid an infinite loop.

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