Electrical – How to properly use packed 2D arrays as input and outputs of verilog task

modelsimverilog

In a part of my verilog project, I am assigning a data to register M[i] by reading from register N[j]. I have written and simulated the code in verilog without any problem. As this particular pattern is repeated many times in a module, I'd like to convert it into a task.
But I'm getting compilation errors when using a 2D array of registers as input and output of the task. Below is a sample code that illustrates the problem.

`timescale 1 ns/100 ps
module test(clk, rst_n);
    input clk, rst_n;
    reg [1:0] idx1;
    reg [2:0] idx2;
    reg [15:0] M[3:0];
    reg [15:0] N[7:0];

    always @(posedge clk or negedge rst_n) begin
        idx1 <= rst_n ? (idx1 + 1) : 0;
        idx2 <= rst_n ? (idx2 + 1) : 0;
    end

    always @(posedge clk or negedge rst_n) begin
        if(~rst_n) begin : reset_registers
            integer i;
            for(i = 0; i < 4; i = i+1) M[i] = 0;
            for(i = 0; i < 8; i = i+1) N[i] = i;
        end
        else begin
            M[idx1] <= N[idx2];
        end
    end
endmodule

The module compiles and simulates as expected now. I would like to convert the segment M[idx1] <= N[idx2]; to a task. So, the new code using a task is:

`timescale 1 ns/100 ps
module test(clk, rst_n);
    input clk, rst_n;
    reg [1:0] idx1;
    reg [2:0] idx2;
    reg [15:0] M[3:0];
    reg [15:0] N[7:0];

    always @(posedge clk or negedge rst_n) begin
        idx1 <= rst_n ? (idx1 + 1) : 0;
        idx2 <= rst_n ? (idx2 + 1) : 0;
    end

    always @(posedge clk or negedge rst_n) begin
        if(~rst_n) begin : reset_registers
            integer i;
            for(i = 0; i < 4; i = i+1) M[i] = 0;
            for(i = 0; i < 8; i = i+1) N[i] = i;
        end
        else begin
            copy(idx1, idx2, M, N);
        end
    end

    task copy;
        input [1:0] x1;
        input [2:0] x2;
        output reg [15:0] A[3:0];
        input [15:0] B[7:0];
        begin
            A[x1] <= B[x2];
        end
    endtask
endmodule

I am getting the following errors when trying to compile it using modelsim:

# -- Compiling module test
# ** Error: D:\projects\test.v(21): Illegal task output argument.
# ** Error: D:\projects\test.v(21): (vlog-2110) Illegal reference to memory "B".
# 
# ** Error: D:\projects\test.v(21): Illegal LHS of assignment.
# ** Error: D:\projects\test.v(21): (vlog-2110) Illegal reference to memory "N".
# 
# C:/modeltech64_10.2c/win64/vlog failed.

Can someone please advise how to use the registers properly in a task? Exactly what is making the statements illegal? Is it even possible to something like this using a task, or is there other way around?
Thank you.

Best Answer

You need to be using SystemVerilog to have unpacked arrays as arguments to a task. And the task as you have written it does not do the same thing as the code without the task. That is because the output array A is uninitialized and you are only setting the value indexed by x1.

Related Solutions

Electronic – How to assign value to bidirectional port in verilog

If you must use any port as inout, Here are few things to remember:

You can't read and write inout port simultaneously, hence kept highZ for reading.
inout port can NEVER be of type reg.
There should be a condition at which it should be written. (data in mem should be written when Write = 1 and should be able to read when Write = 0).

For e.g. I'll write your code in following way.

module test (value, var);
  inout value;
  output reg var;

  assign value = (condition) ? <some value / expression> : 'bz;

  always @(<event>)
    var = value;

endmodule

BTW When var is of type wire, you can read it in following fashion:

assign var = (different condition than writing) ? value : [something else];

Hence as you can see there is no restriction how to read it but inout port MUST be written the way shown above.

I hope that explains it to you.

Electronic – Verilog asynchronous reads of regs – and design question

Your code simulates two multiplexers. These are actually asynchronous components. The fact that Verilog requires data1_temp and data2_temp to be declared as reg's is a quirk of Verilog syntax and your choice of coding style, and doesn't mean these signals would be the outputs of storage elements in a physical implementation.

If you want to capture these values in actual registers, you need to add those explicitly:

reg [7:0] data1, data2;
always @(posedge someclock) begin
    data1 <= data1_tmp;
    data2 <= data2_tmp;
end

But I would like to know what this mini register file would be made of in hardware. Particularly, the 4x8 bit array consisting of k0,k1,k2,k3.

You haven't shown how these variables are assigned, so it's not possible to say how they are implemented. As your code showed, just declaring them as reg doesn't guarantee they are implemented with actual storage elements. If you assign them inside a block that begins always @(posedge clk) then very likely they are flip-flops, but there are ways you could code them that would make them synthesize differently.

I thought when it came to registers and arrays like this, you need a clock to read out data, like RAM?

You need a clock to update a (physical) register. You can read it out at any time. For example:

wire [8:0] sum;
assign sum = k0 + k1;

is perfectly valid code. sum will change whenever any of its inputs changes. If k0 and k1 are the outputs of flip-flops, their values will only change when there is a clock edge.

For another example, you could equally well describe your multiplexers with code like this:

reg [7:0] k0, k1, k2, k3;
wire [7:0] data1_tmp;
reg [1:0] reg1;
// k<n> and reg1 are assigned elsewhere.
assign data1_tmp = (reg1 == 0) ? k0 :
                   (reg1 == 1) ? k1 :
                   (reg1 == 2) ? k2 : k3;

how do I read from this tag_array and do the comparison all within the same clock cycle?

Let me repeat a key point for emphasis: You need to use a clock to assign a new value to a register (an actual hardware register or group of flip-flops). It's output is available at any time.

RAMs are different and how you access the contents of a RAM will depend on details of the type of RAM you use.

I got confused because frankly I don't know enough about memory hardware and how that's possible.

Another key strategy: When you are learning digital logic, I recommend you learn about the physical hardware first, and then work out or study how to simulate it in HDL second. So first, learn what a physical flip-flop is, then learn the standard Verilog methods of describing a flip-flop. Especially if you are trying to write HDL for synthesis, trying to write good code before you learn the capabilities of the underlying hardware will lead you down a lot of dead-end paths.

Best Answer

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