Electronic – Accessing rows of an array using variable in Verilog

rom;verilog

I have a module I'm writing in Verilog that effectively contains a 16 by 10 2D array. At a given point and "row", what I want is to have that data pushed to a net that can be read outside of the module, however, when I attempt to use a variable input to determine which row I want my synthesizer returns these errors:

Error (10734): Verilog HDL error at FontRom.v(12): ROW_NUM is not a constant

The error is pretty clear, but now I'm not sure how I can access different parts of the array if I'm not allowed to use a variable. Also, typically when I need to preload a reg with data I have a reset condition that does it, do I have to do the same thing in this case also? Below is my code. Thank you.

module FontRom(CLK, CHAR_IN, ROW_NUM, DATA_OUT);
   input    wire  [7:0]  CHAR_IN;
   input    wire  [3:0]  ROW_NUM;
   input    wire         CLK;
   output   reg   [0:9]  DATA_OUT;

   parameter   char       = 2'h48;
   parameter   font_value = 40'h000008120481204813FC81204812048120400000;

   reg [0:159] char_font  = font_value;

   always @(negedge CLK)
      if (CHAR_IN == char) begin
         DATA_OUT = char_font[2*ROW_NUM:2*ROW_NUM+10]; // +10 due to Big Endian
      end
      else begin
         DATA_OUT = 8'bZZ;
      end
endmodule

Best Answer

Part selects in Verilog can use variables, as long as the width of the select is a constant. The solution here is to user a lesser-known part select syntax, where you specify the offset and the size.

DATA_OUT = char_font[2*ROW_NUM+:10]; // +10 due to Big Endian

The above selects 10 bits starting at bit 2*ROW_NUM

Excerpt from the SystemVerilog LRM, IEEE 1800-2012

An indexed part-select is given with the following syntax:
logic [15:0] down_vect;
logic [0:15] up_vect;

down_vect[lsb_base_expr +: width_expr]
up_vect[msb_base_expr +: width_expr]

down_vect[msb_base_expr -: width_expr]
up_vect[lsb_base_expr -: width_expr]
The msb_base_expr and lsb_base_expr shall be integer expressions, and the width_expr shall be a positive constant integer expression. Each of these expressions shall be evaluated in a self-determined context. The lsb_base_expr and msb_base_expr can vary at run time. The first two examples select bits starting at the base and ascending the bit range. The number of bits selected is equal to the width expression. The second two examples select bits starting at the base and descending the bit range.

Related Solutions

Electronic – Verilog asynchronous reads of regs – and design question

Your code simulates two multiplexers. These are actually asynchronous components. The fact that Verilog requires data1_temp and data2_temp to be declared as reg's is a quirk of Verilog syntax and your choice of coding style, and doesn't mean these signals would be the outputs of storage elements in a physical implementation.

If you want to capture these values in actual registers, you need to add those explicitly:

reg [7:0] data1, data2;
always @(posedge someclock) begin
    data1 <= data1_tmp;
    data2 <= data2_tmp;
end

But I would like to know what this mini register file would be made of in hardware. Particularly, the 4x8 bit array consisting of k0,k1,k2,k3.

You haven't shown how these variables are assigned, so it's not possible to say how they are implemented. As your code showed, just declaring them as reg doesn't guarantee they are implemented with actual storage elements. If you assign them inside a block that begins always @(posedge clk) then very likely they are flip-flops, but there are ways you could code them that would make them synthesize differently.

I thought when it came to registers and arrays like this, you need a clock to read out data, like RAM?

You need a clock to update a (physical) register. You can read it out at any time. For example:

wire [8:0] sum;
assign sum = k0 + k1;

is perfectly valid code. sum will change whenever any of its inputs changes. If k0 and k1 are the outputs of flip-flops, their values will only change when there is a clock edge.

For another example, you could equally well describe your multiplexers with code like this:

reg [7:0] k0, k1, k2, k3;
wire [7:0] data1_tmp;
reg [1:0] reg1;
// k<n> and reg1 are assigned elsewhere.
assign data1_tmp = (reg1 == 0) ? k0 :
                   (reg1 == 1) ? k1 :
                   (reg1 == 2) ? k2 : k3;

how do I read from this tag_array and do the comparison all within the same clock cycle?

Let me repeat a key point for emphasis: You need to use a clock to assign a new value to a register (an actual hardware register or group of flip-flops). It's output is available at any time.

RAMs are different and how you access the contents of a RAM will depend on details of the type of RAM you use.

I got confused because frankly I don't know enough about memory hardware and how that's possible.

Another key strategy: When you are learning digital logic, I recommend you learn about the physical hardware first, and then work out or study how to simulate it in HDL second. So first, learn what a physical flip-flop is, then learn the standard Verilog methods of describing a flip-flop. Especially if you are trying to write HDL for synthesis, trying to write good code before you learn the capabilities of the underlying hardware will lead you down a lot of dead-end paths.

Creating SRAM array digitally using Verilog

Some tools will infer RAM. They have already thought about area, for example. See your vendor's document for details.

NC-Verilog is for functional simulation. It doesn't track area and timing. For that you need to worry about synthesis to a specific vendor's library.

Analog parts aren't supported by Verilog.

Best Answer

Related Solutions

Electronic – Verilog asynchronous reads of regs – and design question

Creating SRAM array digitally using Verilog

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