You need to give the instance a name (see below)
It also looks like you may be trying to declare it in an always block, this won't work. Declare it outside any blocks (e.g. at the top of the module)
Also, using the "connection by name" (or named association) method of instantiation rather than "connection by order" (or positional association) is less prone to accidental errors from getting the order wrong, especially with modules with many ports.
So the instantiation for connection by name would be
encoder8to3 enc_instance (.A(LL), .B(x), .F(FAULT));
With this method it could be written like this and still be correctly connected:
encoder8to3 enc_instance (.A(LL), .F(FAULT), .B(x));
Whereas using:
encoder8to3 enc_instance (LL, FAULT, x);
would connect B to FAULT and F to x.
Here's a reasonable pdf on modules and instantiating them. I agree good Verilog tutorials are quite thin on the ground (compared to something like C) so starting out can be a bit bewildering.
If you can find a copy at a reasonable price, I do highly recommend the Pong Chu book "FPGA Prototyping with Verilog Examples" I mentioned in my answer to your other question, as well as the focus on synthesis I mentioned, it goes through everything you need to start writing decent code, and is very clear and concise.
There is also a google mailing list for Verilog you might find of use, and fpga4fun has some good tutorials and a forum. And of course there is here :-)
EDIT - about where to declare the module:
The instantiation only connects the ports together, so where you declare it (outside a block) doesn't matter.
If you want to do something with this module inside the always block use some intermediate logic. Create a couple of registers, use the always block to manipulate them as desired, then tie these to the instantiated module ports (in the instantiation).
The way you have it at the moment, the instantiated module can be seen as in parallel with your module rather than inside it, as it just connects directly to the inputs and output of the module. Have a look at the RTL schematic to see what is being generated by the code (under synthesis in the design tab)
Rather than addressing the many problems in your source code, let me just show how I'd implement the module you describe.
First, I wouldn't use a sub-module to build the adder; synthesis tools are perfectly able to create adders from behavioral code. Secondly, an elaborate state machine isn't required; the module can simply produce a final result four clocks after each activation of the start
signal. I've added a done
signal to the module interface to make this explicit.
module seq_mult_4bit (
output [7:0] product,
output done,
input [3:0] a,
input [3:0] b,
input clock,
input start
);
reg [7:0] product;
reg [3:0] multiplicand;
reg [3:0] delay;
wire [4:0] sum = {1'b0, product[7:4]} + {1'b0, multiplicand};
assign done = delay[0];
always @(posedge clock) begin
if (start) begin
delay = 4'b1000;
multiplicand = a;
if (b[0]) begin
product <= {1'b0, a, b[3:1]};
end else begin
product <= {1'b0, 4'b0, b[3:1]};
end
end else begin
delay = {1'b0, delay[3:1]};
if (product[0]) begin
product <= {sum, product[3:1]};
end else begin
product <= {1'b0, product[7:1]};
end
end
end
endmodule
If you really want to use an external module for the adder (which is really the point of your question), simply substitute the wire declaration above with the following block of code:
wire [4:0] sum;
rca_4bit adder (
.sum (sum[3:0]),
.c_out (sum[4]),
.a (multiplicand),
.b (product[7:4]),
.c_in (0)
);
Let me know if you have any specific questions about how this implementation works.
Best Answer
Both are allowed.
Is the 'big endian' convention. However 99.99%** of all Verilog code uses the little endian convention when declaring ports and signals even when building a big-endian processor.
The other convention is that the LS bit has index 0. For example if you have a 32-bit wide address bus the convention is to use:
This does not mean you can't use it. You might want to use only the top 30 bits in a module in which case it is perfectly normal to make an input bus:
In fact when I see that in a module which I get from one of my colleagues (Who all follow these conventions) it tells me that it is a sub-set of a bigger vector.
Last if working with memories (2 dimensional arrays) the index convention is:
I have seen warnings from Cadence compilers if that convention is not followed. I think it happens if you use it in combination with $readmem...
**Rough estimate.