Electronic – Verilog – variable number of inputs/outputs

verilog

Is there a way in verilog to do the following? I have a variable number of FIFOs (1 to 4) created with a generate statement inside of a module

pseudocode:

module()
    generate( for i to NUM_FIFOS )
        FIFO fifoI( args )

What I want to do is have the read data from these FIFOs as outputs of the entire module. Is there a way to have a variable number of output?

e.g.

module(
    generate for( i = 0 to NUM_FIFOS )
        output FIFO_dataI
    )

Thanks for the help!

Best Answer

Use a parametrized bus width:

module FIFO #(WIDTH=8) (
  output [WIDTH-1:0] out,
   /* other ports */
);

Then overwrite the parameter when generating the instances.

module top #(NUM_FIFO=4,WIDTH_FIFO=8)(
  output [NUM_FIFO*WITDH_FIFO-1:0] FIFO_data,
   /* other ports */);
/* ... other code ... */
genvar i;
generate
    for(i=0; i<NUM_FIFO; i++) begin : gen_fifo
        FIFO #(.WIDTH(WIDTH_FIFO)) fifoI (
          .out( FIFO_data[i*WIDTH_FIFO +: WIDTH_FIFO] ),
          /* args */ );
    end : gen_fifo
endgenerate
endmodule : top

Related Solutions

Electronic – Generate gate with a parametrized number of inputs

If I understood your question correctly, I think the following module does what you want. You can very simply specify the gate by its operator (^,&,|, etc) and nothing else. Plus only the desired assignments are generated (which is I think what you are looking for).

`timescale 1 ns / 1 ps

module selectable_gate(input [7:0] in, output out);

parameter [7:0] SELECT = 8'b10010100;

function integer count_ones;
  input [7:0] v;
  integer ret;
  integer i;
  begin
    ret = 0;
    for(i=0;i<8;i=i+1) begin
      if (v[i]) begin
        ret = ret+1;
      end
    end
    count_ones = ret;
  end
endfunction

function integer nth_one;
  input integer n;
  input [7:0] v;
  integer i,ret,cnt;
  begin
    ret = -1;
    cnt = 0;
    for(i=0;i<8;i=i+1) begin
      if (v[i]) begin
        if (cnt == n) begin
          ret = i;
        end
        cnt = cnt+1;
      end
    end    
    nth_one = ret;
  end
endfunction

localparam integer w = count_ones(SELECT);
wire [w-1:0] y;

generate
  genvar i;
  for(i=0 ; i<w ; i=i+1) begin
    assign y[i] = in[nth_one(i,SELECT)];
  end
endgenerate

assign out = ^y; // specify gate here (e.g. ^y, &y, |y, etc)

endmodule;

The above module for the default SELECT = 8'b10010100 should end up generated as:

assign y[0] = in[2];
assign y[1] = in[4];
assign y[2] = in[7];
assign out  = ^y;

Which is the same as xor(in[2],in[4],in[7]).

Since genvars are always unrolled as constants inside the generates, the trick was to find constants that allow the proper conditions for the generate, and use functions for any temporary variable manipulation necessary to calculate them.

Using ‘$display’ in Xilinx (verilog)

I made the necessary change and put the '$display' inside the modules. But this the output i am getting: 0 alumod A_in=xxxxxxxxxxxxxxxx, B_in=xxxxxxxxxxxxxxxx, ALU_out=xxxxxxxxxxxxxxxxx Why am i not getting the output?

because you haven't provided any test input values. For example, in your testbench A_ALU and B_ALU aren't initialized. Since nets that are driven get the default value of 'x', you are getting A_in & B_in as x's.

I've simplified your code here. See the testbench code where A_ALU & B_ALU values are provided. The '$display' is used in the 'alumod.sv' file. After simulating you'll get output like this:

#                  100 alumod A_in=x, B_in=x, ALU_out=x
#                  105 alumod A_in=1010, B_in=1010, ALU_out=10100
#                  110 alumod A_in=1010, B_in=10100, ALU_out=11110
#                  115 alumod A_in=1010, B_in=11110, ALU_out=101000
#                  120 alumod A_in=1010, B_in=101, ALU_out=101
#                  125 alumod A_in=1010, B_in=100, ALU_out=110

See, for 1st 100ns the values are x since they aren't initialzed yet.

Best Answer

Related Solutions

Electronic – Generate gate with a parametrized number of inputs

Using ‘$display’ in Xilinx (verilog)

Related Topic