I am trying to write a testbench for a 16-bit RISC processor using verilog in Xilinx.
I have the following modules:

- TOP
    -datapath
       -instruction_fetch
            -program_counter
            -instruction_memory
            -instruction_register
       -MUX21
       -alu
       -MUX41
       -general_purpose_reg
       -data_memory
    -control_unit

My question is : To get this to work do i need to create just one test bench for the 'TOP' module and have '$display' statements for each module inside it?

FOR EXAMPLE, if i have to display output of the alu module then should I have the display statement in the test bench for TOP?

module top_test;

    // Inputs
    reg clk;
    reg rst;
    reg start;

    // Outputs
    wire [4:0] PS;
    wire [3:0] opcode;
    wire [15:0] PC;
    wire [15:0] IM_instr;
    wire [15:0] IR_instr;
    wire [14:0] CV;
    wire [15:0] R1_reg;
    wire [15:0] R2_reg;
    wire [15:0] R3_reg;
    wire [15:0] R4_reg;
    wire [15:0] R5_reg;
    wire [15:0] R6_reg;
    wire [15:0] R7_reg;
    wire [15:0] R8_reg;
    wire Z;
    wire [15:0] A_ALU;
    wire [15:0] B_ALU;

    // Instantiate the Unit Under Test (UUT)
    TOP uut (
        .clk(clk), 
        .rst(rst), 
        .start(start), 
        .PS(PS), 
        .opcode(opcode), 
        .PC(PC), 
        .IM_instr(IM_instr), 
        .IR_instr(IR_instr), 
        .CV(CV), 
        .R1_reg(R1_reg), 
        .R2_reg(R2_reg), 
        .R3_reg(R3_reg), 
        .R4_reg(R4_reg), 
        .R5_reg(R5_reg), 
        .R6_reg(R6_reg), 
        .R7_reg(R7_reg), 
        .R8_reg(R8_reg), 
        .Z(Z), 
        .A_ALU(A_ALU), 
        .B_ALU(B_ALU)
    );

    initial begin
        // Initialize Inputs
        clk = 0;
        rst = 0;
        start = 0;

        // Wait 100 ns for global reset to finish

    #100 ;
    rst = 1;

//  $display($time, " alumod A_in=%b,B_in=%b,ALU_out=%b", A_in, B_in, ALU_out); 
    end 

    always
       begin 
          #5 clk = !clk;
         end



endmodule

alu module code :

module alumod(clk,rst,load_SR,ALU_opcode,A_in,B_in,ALU_out,data,carry,Z);

    input clk,rst;
    input [15:0] A_in,B_in;
   input [2:0]  ALU_opcode;
    input load_SR;

   output [16:0] ALU_out;
    output [15:0] data;
    output carry, Z;

   reg [16:0] ALU_out;
    reg Z;

    always@(ALU_opcode or A_in or B_in)

    case(ALU_opcode[2:0])

    3'b000:  ALU_out = A_in + B_in;
    3'b001:  ALU_out = A_in - B_in;
    3'b010:  ALU_out = {{16{A_in[15]}},A_in} >> B_in; //ARITHMETIC 
    3'b011:  ALU_out = A_in << B_in;            //LOGICAL LEFT SHIFT
    3'b100:  ALU_out = A_in >> B_in;            //LOGICAL RIGHT SHIFT
    3'b101: if (A_in < B_in)                                    //SLT
                    ALU_out = 1;
               else 
                    ALU_out = 0;
   3'b110:  ALU_out = ~A_in;                    //INV
    //'b111: HAMMING DISTANCE


    //default: alu_out = ;
    endcase

// Z REGISTER MODULE
always@(posedge clk or posedge rst)
        if(rst)
            Z <= 1'b0;
        else if(load_SR)
            Z <= (data == 0);
        else 
            Z <= Z;

        assign data =  ALU_out[15:0];
        assign carry =  ALU_out[16];



endmodule