Electronic – Number of I/O pins in Xilinx Virtex 5

I would not use an FPGA.

You mention you have no experience with FPGA's, and yet you are interested in doing digital signal processing on an FPGA... numerical manipulation + signal processing are difficult enough to get right on a computer/DSP/microprocessor, where the programming tools are conventional programming. It seems to me that using a digital signal processing project for a first FPGA project is likely a recipe for frustration.

If you want to learn FPGAs, try doing something more suited to the development tools, like state machines or communications packet processing.

For a DSP project like what you've described, I'd recommend a DSP or a Cypress PSOC or an Analog Devices Microconverter (=microcontroller with ADC+DAC builtin) instead.

(full disclosure, which provides some context for my advice: I do not use FPGAs myself. I have used programmable logic = PLDs on rare occasions. My officemate does use FPGAs frequently, and I've seen enough VHDL/Verilog code looking over his shoulder to know that it is well suited for bit manipulations. He is a seasoned engineer with lots of experience with FPGAs; in a recent conversation with him where he was doing some fairly simple math on integers with different bit widths, I told him he needed to do sign-extending on the shorter bit width number in order to subtract it properly, and he got this look on his face, like "oh man, I don't want to have to do sign extension..." Adding and subtracting is not very hard in an FPGA. Beyond addition and subtraction, you really need to know the tools and libraries. And floating-point processing??!?!!??!?!!?)

Your design will not function correctly if it runs at 100 MHz but is only spec'd (by the tools) to run at 50 MHz. If it does, then it's a one-off miracle that wouldn't work when you make a change and rerun the tools. Don't do it. Don't even do it if your clock is 100 MHz and the tools tell you the design can run at 99.5 MHz.

To solve your problem you can either write a simple 'divide by power of 2' clock divider to reduce the clock frequency (something like this in Verilog):

reg [n:0] count; 

always @(posedge CLK_100) begin
  count <= count + 1;
end

BUFG bg_0 (.I(count[m]), .O(CLK_DIV));

(where 'm' <= 'n' and 'bufg' is a global clock buffer, and must be used for synchronous designs) or use a Digital Clock Manager (DCM).

Hopefully that solves your pipelining issues as well unless you absolutely have to run the entire design at 100 MHz. Other than pipelining you can consider using FIFOs if you have part of the design running at 50 MHz and the other at 100 MHz, but you'll have to say a bit more about what you're doing to get more meaningful help here.