Square law device using FPGA

fpgaverilog

I am trying to implement Square Law Device on Virtex 5 Family FPGA but before burning it to the FPGA I was trying to simulate it in the Xilinx ISE kit. I am not sure whether the code is correct or not but here is the procedure I followed:

  1. Created the schematic
  2. Generated and Instatiated the IP Cores for Binary Counter (just for simulation purpose) and Sine Wave Generator using Cordic
  3. Inserted a Verilog Test Fixture.

But I was not successful in simulating it. I am inserting the code for the Verilog Test Fixture.

// Verilog test fixture created from schematic F:\Xilinx\demod\demod\schema.sch - Wed May 01 19:16:25 2013

`timescale 1ns / 1ps

module schema_schema_sch_tb();

// Inputs
   reg clk;

// Output
   wire [35:0] outp;

// Bidirs

// Instantiate the UUT
    schema UUT (
    .outp(outp), 
    .clk(clk)
   );

// Initialize Inputs
   `ifdef auto_init
         initial begin
             clk = 0;
                 repeat(100) begin
                     #10 clk = 1;
                     #10 clk = 0;
                 end
         end         
   `endif
endmodule

Also I am copying the schematic of the project.

Schematic of the Project
Where am I wrong?

Edit: The multiplier element is red just because it got selected while taking snapshot. I tried removing the instiantion of IP cores and I got some output but not the correct one. After that I replaced the always begin loop with repeat(16) begin loop, but it shows an error near repeat.

Best Answer

Your initial begin block does not have an end, so you're getting a syntax error.

If you see errors past this, then please put the full text of the error into your question.

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