I don't know what your budget is, but Digilent have quite a couple of different boards - and also offer student discounts. We used the Spartan3/3E starter boards and the Nexys2 boards at my university.
A Spartan3/6 board would allow you to do all the basic stuff, and the Xilinx ISE Webpack software suite used for programming it is freely available.
All of the DCM blocks (digital clock managers) in FPGAs I've worked with can scale up and shift clock frequencies cleanly. Ensure that your input base clock arrives on a specific clock pin if you can, as this will introduce the least skew routing to the dcm.
If you want more specific guidance, which part are you targeting and what frequencies? If you are targeting Ghz for instance on a cheap part, it probably isn't going to happen.
The DCM blocks often have multiple outputs that can be driven to different frequencies from the same base clock, so all your generated clocks can have a common duty and phase.
Edit: I see the sorry history of your previous questions clocking on spartan6 FPGAs and Spartan 6 DCM unstable clock output - Please link the questions in future.
As other commenters have noted, what you are asking is impossible in the general case. A clock management unit cannot be both stable (rejecting noise on the base clock) and respond to linear/step changes in the input quickly. These are contradictory design goals.
If I were you, I'd settle for a nice stable, fixed clock coming into the FPGA, and then re-program the DCM module's output clock ratios using logic in your design. I know offhand that the StratixV parts have a bus into the DCMs to allow ratio and phase changes while operating. This should avoid the need to settle and lock the input clock each time.
Whatever feedback or user interface you use to make these adjustments would then be done by the FPGA, e.g. decoding UART instructions from a PC or scanning keypad/switches.
Have a look at this Xilinx App Note, it suggests the Spartan 6 PLLs do have a dynamic reconfiguration port for doing this sort of thing: http://www.xilinx.com/support/documentation/application_notes/xapp879.pdf
Update:
If for some reason you really need to have the input coming from a varying clock, you may choose to design an input stage that measures the frequency of the input clock against some stable base clock, measuring the frequency shift (in Hertz) and uses this to dynamically reprogram the DCM. This is advanced stuff, theres probably only a few dozen engineers in the world who use the dynamic ports on FPGAs. It may need some analogue design, eg. an external beat-mixer/Heterodyne first to get enough resolution on . Expect to have to raise a few queries with Xilinx to get it all working.
Best Answer
The short answer is yes, although it's really not a good fit for an FPGA project and the FPGA is mostly useless.
Fundamentally a Theremin is a capacitative sensor device like a smartphone's touchscreen or proximity sensor, but tuned to very high sensitivity. See this Arduino theremin, which would be a good basis to adapt from. There may be capsense libraries or IP cores for your FPGA which would make is easier.