memory
Gameboy cartridges, without memory banking, have 32KB of ROM and no RAM. To have more, carts tend to use a MBC (Memory Bank Controller) IC to add RAM and ROM, among other things.
However, two cartridge types, 8 & 9 (08h ROM+RAM 09h ROM+RAM+BATTERY) don't seem to have an MBC.
How do types 8 & 9 work?
You don't need dual-port RAM or even a serial RAM with two interfaces; For SPI it's a little trickier, but I2C allows multiple masters "out of the box." Either way, your software will have to monitor the bus conditions to see if it lost the bus and if so, wait for another opportunity.
For SPI, the MOSI, CS and CLK lines must be tri-stated (or open-collector) with pull-up resistors to keep the lines from floating. You will also need some kind of bus arbitration. This can be as simple as a single GPIO between the two masters so that the one with higher priority signals the lower-priority master that the bus is unavailable, but a more elegant solution would be a single open-collector line between the masters. When the bus is idle, neither master is yanking the line down so it floats high with a pull-up. The logic is that if the line is high, the bus is available. The master that wants to use the memory would look at the "bus available" line and if it's high, drive the line low and wait a few ms to make sure the other master didn't grab the bus at the same time. If the RAM SPI CS line is still inactive, it can be safe to assume that the bus is yours. Do the transfer, tri-state your MOSI/CLK lines and let go of the "bus active" signal.
The "wait a few ms after yanking the bus request line low" is necessary since it is possible for both masters to grab the line at the same time.
If you are only ever using one shared device and that device does not require multiple transfers, you could use its CS line as the "bus available" signal, but this isn't quite as robust.
Memory cells are arranged in a matrix
This is a 16-bit memory, 1 bit wide, so it needs 4 address lines to address each individual bit. That's the a3..a0 lines at the left. a0 and a1 enter the green 2-to-4 demultiplexer. An N-input demultiplexer can have 2\$^N\$ output lines, and the binary input indicates which of those will be active. That's the row select.
The column select does something similar, but uses a multiplexer to select 1 of 2\$^N\$ lines as the output signal. So the combination of row select and column select can address an individual memory cell.
This is Random Access Memory because any bit is directly accessible, no matter what the address is. And it goes for DRAM as well as SRAM. SRAM needs more hardware to store a bit (4 or 6 FETs) than the DRAM shown, which needs only 1 FET per bit. The data is stored in the capacitors. Capacitors have leakage, and after some (very short!) time the data will be gone. That's why DRAM needs frequent refreshing: the data is continuously read and rewritten between accesses. This adds some extra hardware to the device, but a DRAM die is still much smaller than an SRAM die with the same capacity.
Best Answer
The cart connector has a pin (which seems to be variously reffered to as "MREQ" or CS_SRAM) which distinguishes between access to the cart rom space and access to the cart ram space. I'm seeing conflicting information on line about the active polirity of this line so it may be nessacery to do some testing.
If you can find a rom and ram chip with the right chip select polarities you may just be able to hook them up directly. If the chip select polarities on your chips are wrong you may need an inverter. Definately no need for anything as complex as a memory bank controller just to have both rom and ram.