Let's say that we want to do a good job of testing this, but without going through the entire 2^32 space of possible operands. (It is not possible for such adder to have such a bug that it only affects a single combination of operands, requiring an exhaustive search of the 2^32 space, so it is inefficient to test it that way.)
If the individual adders are working correctly, and the ripple propagation between them works correctly, then it is correct.
I would giver priority to some test cases which focus on stressing the carry rippling, since the adders have been individually tested.
My first test case would be adding 1 to 1111..1111 which causes a carry out of every bit. The result should be zero, with a carry out of the highest bit.
(Every test case should be tried over both commutations: A + B and B + A, by the way.)
The next set set of test cases would be adding 1 to various "lone zero" patterns like 011...111, 1011...11, 110111..111, ..., 1111110. The presence of a zero should "eat" the carry propagation correctly at that bit position, so that all bits in the result which are lower than that position are zero, and all higher bits are 1 (and, of course, there is no final carry out of the register).
Another set of test cases would add these "lone 1" power-of-two bit patterns to various other patterns: 000...1, 0000...10, 0000...100, ..., 1000..000. For instance, if this is added to the operand 1111.1111, then all bits from that bit position to the left should clear, and all the bits below that should be unaffected.
Next, a useful test case might be to add all of the 16 powers of two (the "lone 1" vectors), as well as zero, to each of the 65536 possible values of the opposite operand (and of course, commute and repeat).
Finally, I would repeat the above two "lone 1" tests with "lone 11": all bit patterns which have 11 embedded in 0's, in all possible positions. This way we are hitting the situations that each adder is combining two 1 bits and a carry, requiring it to produce 1 and carry out 1.
When the inputs \$\small{\text{A}}\$, \$\mathsf{\small \overline{\text{A}}}\$, \$\small{\text{B}}\$, and \$\mathsf{\small \overline{\text{B}}}\$ are latched in, they create four minterms \$\mathsf{\small \overline{\text{A}}}\$ ⦁ \$\mathsf{\small \overline{\text{B}}}\$, \$\small{\text{A ⦁ B}}\$, \$\mathsf{\small \overline{\text{A}}}\$, and \$\mathsf{\small \overline{\text{B}}}\$ which are generated vertically using a wired-AND configuration as described in the patent.
Two outputs are then generated: SUM = \$ \overline{ (\small \overline{\text{A}} ⦁ \small \overline{\text{B}}) + (\small {\text{A}} ⦁ \small {\text{B}}) }, \$
and
CARRY = \$ \overline{ \small \overline{\text{A}} + \small \overline{\text{B}} } \$
because the outputs are generated horizontally using a NOR function as described in the patent.
Then using De Morgan's laws, The first equation simplifies to A xor B, and the second to A ⦁ B which are the definition of a half adder.
You can verify this by typing "simplify not((not a and not b) or (a and b))" into WolframAlpha for the first equation, and "simplify not(not a or not b)" for the second.
Best Answer
I don't have this book.
The "decoder" transforms opcodes into signals for driving the various execution units (alu, branch, ...) and selecting the registers.
Tranditional RISC CPUs have relatively simple encodings where there are almost fixed fields for selecting the operations. This is far less true in CPUs like x86.
(Example, some MIPS instructions : http://www-inst.eecs.berkeley.edu/~cs150/sp11/checkpoint_1/images/MIPS150ISA.png)
Then, for the arithmetic/logic part, there is not separate adder, subtractor, and, or... blocks selected with multiplexers. Many operation are combined in multipurpose circuits, for example adder/subtractor/negate.