How to calculate power requirements of LED matrix, per row or per LED

I would suggest that you should use a shift-register chip that has decent current-sinking capability for the cathodes, and use a shift-register chip to drive discrete transistors for the anodes. Perhaps wire the matrix as 7x26 and use two TLC5925 chips for the columns, and use a 74HC164 or equivalent to drive seven nice beefy transistors for the rows.

Actually, it may be a good idea to rig up the rows with a counter chip and a 555-timer wired so that they will automatically scan, but the main processor can 'nudge' the timer when it's almost ready for its next count. Such a circuit could ensure that no matter what the processor did, it would not be possible for a row to be energized much more than 1/5 of the time (the processor could strobe six rows quickly, then linger on the seventh, then six rows quickly, linger on the seventh, etc. but the hardware would limit what fraction of the time would be spent on any one row even in a worst-case situation.

As the number of shift registers grows, it will become necessary to shift data through them faster in order to achieve a particular frame rate. This will in turn increase the amount of current required by each shift register.

It would probably be a good idea to use a partially-parallel arrangement. If the CPU can clock out eight or sixteen bits in parallel, that will reduce by a factor of eight or sixteen the number of bits that have to go through each shifter. It may also be useful to design a circuit which will take every eight or sixteen bits shifted in and send one to each of eight or sixteen shifters. Applying such circuits even one or two deep will greatly minimize the number of rapidly-switching signals required.

My inclination would probably be to use boards of e.g. 64x8 LEDs, multiplexed 64x8. Boards could be chained to a certain depth, but I probably wouldn't recommend chaining all 64 boards together. If the goal is a 128x64 grid, it might be reasonable to have eight pairs of 64x8 boards chained together, and output one bit to each pair simultaneously (so 128x8 bits for each 1/8 frame). I would suggest that the mutliplex timing be controlled by a master device, but each 8x64 panel should include its own row drivers along with some circuitry to limit each row's duty cycle to a maximum of 16% or so (when all is working properly, the duty cycle should be 1/8).