How to concatenate unsized parameters

synthesisverilog

My verilog module is instantiated in a VHDL top entity. I want to pass integer design-time configurations to the verilog module. These are the initial configurations that should appear at reset.

module abcmod
#(
  parameter  [23:0] VT_PARAM1           = 1280,
  parameter  [7:0]  VT_PARAM2           = 53,
 ..
)
( .. );

reg [31 : 0] params; 

always @( posedge Clk )
  begin
    if ( Resetn == 1'b0 )
      params <= {VT_PARAM1,VT_PARAM2}; //Assign default 32-bits
    ..

The above examples compiles with Xilinx ISE 14.4, but does not function. VHDL parameters are not passed to verilog parameters with [L-1:0]. Only parameters with unsized parameter par_name = DEF_VALUE, format works.

So I have to pass integer parameter values, unsized, then verilog should expand them to 24 and 8 before concatenate them. How could I possibly do this?

Best Answer

You can SHIFT and OR them

params <= (VT_PARAM1 << 8) | VT_PARAM2; //Assign default 32-bits

Related Solutions

Electronic – Concatenate signal n times in Verilog

This is what I did to repeat and concatenate n times:

{n{VARIABLE}}

Example:

module concat_n(dummy,super_dummy,clk);

input [7:0] dummy;
input clk;

output [23:0] super_dummy;

wire [7:0] dummy;
reg [23:0] super_dummy;

always @(posedge clk)
  super_dummy <= {3{dummy}};

endmodule

Simulation:

   module test;

  initial begin

     $dumpfile("test.vcd");
     $dumpvars(0,test);

    dummy_in = 8'b10101111;
    #10 dummy_in = 8'b10101010;
    #10 dummy_in = 8'b11110001;
    #10 dummy_in = 8'b01010011;
    #10 dummy_in = 8'b00111100;
    #10 dummy_in = 8'b00110011;
    # 1 $finish;
  end

  reg clk = 0;
  always #1 clk = !clk;

  wire [23:0] super_dummy_out;
  reg [7:0] dummy_in; 

  concat_n concat_3 (dummy_in, super_dummy_out, clk);

  initial
     $monitor("At time %d, dummy_in = 0x%h, super_dummy_out = 0x%h ",
              $time, dummy_in, super_dummy_out);
endmodule

Simulation Result: Edit had to be at least 6 chars

Electronic – concatenate inputs in verilog

wire [15:0] joined;
assign joined = {AS_1, AS_2};

That creates a wire which always has the joined value.

The braces can be used in most places to concatenate values like this.

Best Answer

Related Solutions

Electronic – Concatenate signal n times in Verilog

Electronic – concatenate inputs in verilog

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