How to know if the ESP8266 has been manually reset

Yes, you can use the analog to digital converter on pin 1 even if the external reset is still enabled on that pin as long as the voltage on that pin does not drop below the reset threshold.

Here is a simpler version of your circuit that works reliably...

^{simulate this circuit – Schematic created using CircuitLab}

...

When the button SW1 is pressed, the resistors R2 and R1 form a voltage divider that puts about 4.54 volts onto pin RST.

Here is an Arduino test program that will light the onboard LED when ever the button is pressed...

int led = 1;    // Onboard led on trinket

setup() {
    pinMode( led, OUTPUT );
}

loop() {
    if (analogRead(0)) > 900 ) {   // reset pin is near Vcc
        digitalWrite( led , 0 );   // turn led off
    } else {                       // reset pin is less than 900/1024 * 5 vcc
        digitalWrite( led , 1 );   // turn led on
    }
}

Notes:

A Trinket is basically just an ATTINY85 that has a USB connector and a preloaded bootloader so it is easy to get code into it using the Arduino IDE. Everything said here about the Trinket goes for a bare ATTINY85 and vice versa.

The datasheet for the ATTINY85 specifies the minimum voltage on the Reset pin that will interpreted as "1" as 0.9 volts * (V_IH2), which comes out to 4.5 volts. Since the ~4.54 volts output by out voltage divider is higer than that, it should be seen as a "1" and not reset the chip.

There is 30k-60k built in pullup on the reset pin, so we could in principal just use, say, a 30k ohm R2 and not need R1 but I've found that you can get spurious resets from switching noise with only the internal pullup.

I picked 10k & 1k ohm resistors because they are common and provide enough current reliably work, but only waste about 2mA when the button is pushed. Very little current is used when the button is not pressed.

I picked 1000 as the threshold value on the analogRead because it gives plenty of headroom on both side for inaccuracies in the values of the two resistors. When the button is not pushed, the reset pin should be very near Vcc and so the analogRead() should be very near 1023. When the button is pushed, the voltage on reset will be pulled lower by R2, but exactly how much lower depends on the exact values of R1 and R2 (resistors' actual value can be quite different from their market value due to tolerance) and the internal pull-up, so I picked a higher value than just the midpoint.

Added:

An XOR (Exclusive OR) gate (or XNOR) can be used to produce an output pulse on the rising or falling edges of an input signal. An XOR 'truth table' is:

IN Out

00 0
01 1
10 1
11 0

ie - the output is high when one only input is high. Both inputs low or both inputs high produce a low output.

In the diagram below the RC combination acts as a delay that causes any input level change to be delayed in arrival time at the RC connected input relative to the directly connected input. When a continuous high or low is input, both XOR inputs are the same polarity and output is low.
When the input level transitions there is a period of about t = R1 x C1 when the two inputs are not the same and an output pulse is produced.
Ideally Schmitt triggered inputs would be used, but std inputs "work OK" - subject to there being no input transients.

The RC only consume energy when the capacitor charges or discharges and this can be very small so the circuit achieves extremely low power consumption. CMOS gates when not switching draw sub microamp currents.

You can get single XOR gates in a package so small it's almost a breathing hazard. One of many is 74AHCT1G86SE-7

^{simulate this circuit – Schematic created using CircuitLab}

______________________________

Something as simple as this may work for you depending on overall application (as sometimes unspecific "extras" complicate the requirement).

This shows the general principle and you may have to 'play' somewhat.

/RST is assumed to have an internal pullup to Vdd. If not, one can be added.

Initially, SW1 open = uC sleeping.
SW1 closed = /RST low and Cd is charged low. SW1 open releases /RST and processor come out of sleep.
Cd level can be read via GPIO.
Cd level returns to Vdd = high after a period > t= RdCd.

If the switch is the only thing that brings the processor out of sleep then the GPIO read and no circuitry is needed except apart from the switch and a pullup for /RST (internal or external).

^{simulate this circuit}