I have an RTL simulation where module TB is the testbench for module A.
Module A generates $fatal when it meets some condition it doesnt like.
Module TB generates/collects transactions to/from A. Is there a way I can trap $fatal or $error statements in module TB ?
I am looking to add a few lines in TB like
always @*
begin
if (FATAL_CONDITION_SEEN) begin
log("there was a problem");
end
end
Ideas ?
Best Answer
SystemVerilog has a
final
block that is triggered by the end of simulationYou can have as many final blocks as you want, but like
initial
blocks, there is no guaranteed order among them. There are restrictions about what you can put in afinal
block, like no time consuming statements. See the 1800-2012 LRM section 9.2.3 Final procedures