If I want to delay my FSM to stay in a state for 5 cycle how could I do that?
I suppose I should use a counter but what is the VHDL code how could I use a counter inside the process statement.
Sorry if the question is simple I am learning VHDL coding.
I am using this coding, but it is not compiling :
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity state3_fsm is
port (
clk_H : in std_logic;
res_H : in std_logic;
start : in std_logic;
done_H : in std_logic);
end entity state3_fsm;
architecture arc of state3_fsm is
type statetype is (s0, s1, s2);
signal pr_state, nx_state : statetype;
signal count : std_logic_vector(3 downto 0);
begin
ff_pro : process (clk_H, res_H)
begin
if (res_H = '1') then
pr_state <= s0;
elsif (clk_H'event and clk_H = '1') then
pr_state <= nx_state;
end if;
end process ff_pro;
com_pro : process (start, count, pr_state, done_H)
begin
case pr_state is
when s0 =>
if (start = '1') then
nx_state <= s1;
else nx_state <= s0;
end if;
when s1 =>
count <= count + 1;
if (count = 5) then
nx_state <= s2;
count <= "000";
else
nx_state <= s2;
end if;
when s2 =>
if done_H = '1' then
nx_state <= s0;
else nx_state <= s2;
end if;
when others =>
nx_state <= s0;
end case;
end process com_pro;
end architecture arc;
Best Answer
What you have is on the left, and what you want is on the right assuming you want a delay between State 2 and State 3. You simply can add a new state that handles the delay.
Some pseudo code for the delay state would be implemented like the following:
If clk happens every 50ns, you just created a 250ns delay. You're trapped in this state until you've met the delay, then you hop into the next state you want.
EDIT: Just reread your question and maybe I misunderstood but the concept is the same anyways. If you want State 3 to happen 5 times you would put a block in State 3 that points to State 4 based on a variable counting up to 5, and State 4 just sends you back to State 3 or State X based on that variable.