Have you looked at the datasheet of the 4046 PLL ? The 4046 contains both types of PD.
The type-1 PD implemented as an XOR outputs 0 when both it's input signals are equal and outputs a 1 when they are not. It cannot distinguish between both signals so it cannot detect if Fvco is too high or too low. It can only detect that it is "not the same" as Fin.
At phase = π the signal inverts so at phase = π - delta the PD's output signal is the same as what it is at phase = π + delta. This explains the positive slope changing to a negative slope at phase = π. The input signal inverts but the XOR treats it the same way, it cannot do any better !
"Why would a PLL with this type of PD not lock if the phase difference input to the PD is greater than 2π?"
Your assumption is wrong, it does lock.
Let me explain:
I give you two signals and a 4 channel oscilloscope.
At t = 0 I provide you with 3 signals:
signal A is a 1 kHz sinewave starting at phase = 0
signal B is a 1 kHz sinewave starting at phase = π
signal C is a 1 kHz sinewave starting at phase = 10 π
Now tell me which signal is which !
Think about it before reading any further !
The answer is that you can only tell me which is signal B.
You cannot distinguish signals A and C because a sinewave repeats
itself every 2π of the phase.
Like you, a type-2 PD also cannot distinguish signals which are shifted by 2π
so it will treat a phase of delta the same as a phase of delta + 2π
or delta + 4π. That is why the graph only shows 0 to 2π, the graph repeats itself every 2π just like a sinewave.
It can however distinguish a phase of π - delta from a phase of π + delta !
That is it's advantage over a type-1 PD.
For a type-2 PD it is not the absolute phase that is locked, it is the modulo(2π) of that phase and that is OK as the signal repeats.
One option is using a DDS that can reach 1.2 GHz, with a frequency doubler.
Doublers are essentially just some nonlinear circuit to produce harmonics with some filtering to pick out the preferred 2nd harmonic at the output, so they don't require any lock-in time when changing frequency (aside from that implied by the bandwidth of the selection filter).
Doublers tend to allow at least a bit of the input frequency (perhaps 20 dB or so below the 2nd-harmonic output), and also its 3rd harmonic, through to the output, so some careful filtering, or even an adjustable filter, might be required if you need a very pure output frequency.
Doublers also tend to be a bit fussy about the power level at the input, and produce an output attenuated from the input level, so you may need some additional amplification and/or attenuation to get the scheme working well.
Two application circuits are given in the [AD9566] datasheet... What would be the switching time from, say 1.6 to 2.4 GHz for these?
Those are both essentially PLL schemes. The switching time will be limited by the bandwidth of the loop filter. I'd expect it to be difficult to get it below a several 10's of ns. Although 50 ns doesn't seem totally out of the question if the loop bandwidth can be as high as 20 MHz. (This also applies to your proposal of a straight PLL solution)
Best Answer
Assuming a maximum frequency of ~4GHz you could cascade three of these x4 ECL divider chips (SY10100EP33V), by a total 4x4x4=64 division ratio. They are not programmable, so they are simple to use, just like flip-flops. Enough to bring the frequency to a more manageable ~63MHz.
Further division can then be achieved using a plain binary counter of a common logic family, like the 74HC4060 which can work safely up to ~80MHz if powered at 5V. It has an internal 14-stage counter, so it can divide by a maximum factor of 2^14=~16,000, enough to perform the division to any lower frequency you would want.
Of course you might have to design a proper interfacing circuit between those ECL chips and the HC counter: the logic levels might not be compatible by direct connection, study the datasheets carefully. Anyway the "4060" counter is a fairly common part also in other CMOS families (AC,LV, etc.), so you can search analogous parts (e.g.: 74LVC4060, 74AC4060, etc.) and see if their logic levels are better suited for direct connection with ECL outputs.