Interfacing memory to papilio fpga board

Here's how I'd do it...

I would start with a Xilinx Spartan-6 FPGA. The reason I'd go with this is because they have "hard cores" for a DDR-SDRAM interface. By hard core, I mean that the circuitry for this memory interface is a dedicated chunk of logic and not in the normal "user programmed fabric of logic". This means that you're going to meet timing, and you don't have to write this logic on your own.

Next, I'd hook up some DDR2 SDRAM to the part. DDR2 SDRAM is fairly inexpensive, easy to get, and certainly fast and large enough for what you want to do. I'd start with a 16-bit wide data bus, and increase that if you need more speed. You can use the Xilinx CoreGen or Memory Interface Generator to get your DDR2 interface core.

The rest is "relatively easy", in that it's just moving data around and generating the proper sync pulses.

One major down-side to this approach is that you're basically limited to using BGA's for both the memory and FPGA. One plus side is that there are FPGA development boards that already have this circuitry on it.

Now that question will open a can of worms! Basically, there is no way to accurately answer that question because there are so many factors involved. That being said...

The "quick" answer is that I wouldn't be concerned until the signal frequencies get near 1 MHz. Between 1 and 10 MHz I would be extra careful. And above 10 MHz I would have a PCB made. Of course there are exceptions, and this is what I would do, etc. But as a rough order of magnitude place to start, it works.

There are many issues involved with this, and I'll try to cover them here...

As others have stated, it's not the signal frequency but the rise/fall time of the signal edges. If you can slow down the edges (but not too much) then you'll have an easier time. FPGA's are great for this because you can change the slew rate and drive strength of the I/O Pins. In a synchronous system, this is more important on the clock lines than the data lines (I'm not saying that data isn't important, however.)

While doing proper signal termination is important, you can't do signal termination without knowing the characteristic impedance of the wire. And in a breadboard type system you won't know what the impedance is, no matter how hard you try. In this case, you'll simply end up twiddling with it until it just happens to work.

Pay attention to the signal return paths and loop currents. This is going to play the biggest part in making the system run fast. Of course, this is damn near impossible to do correctly with a breadboard, but those are the breaks. This is why people use power/gnd planes and 4+ layer PCB's.

I've ran PCIe (2.5 GHz) over wire-wrap-wire for about 5 inches. And I've ran PCIe over a "commercially available" wire for 12 inches. So you can get good performance from wire. It's all in how you use it.

A good breadboard can probably run faster than a bad 2-layer PCB.

Of course, most modern parts are in packages that require a PCB.