Feedback Loop – Issues with Program Counter Input to Output

Turns out I missed a crucial detail in the accompanying text, and the registers are indeed composed out of two (master-slave) sub-registers:

The Use of Master–Slave Registers

Note that the contents of the PC are incremented within the same clock pulse. As a direct consequence, the PC must be implemented as a master–slave flip–flop; one that responds to its input only during the positive phase of the clock. In the design of this computer, all registers in the CPU will be implemented as master–slave flip–flops.

To understand the behaviour of the CPU you need to know how an instruction is made: there is a fixed part that represent the instruction (let's say that 0001 stands for INC), that is repeated every time you write an INC instruction, and there is a part that depends on the instruction and it's why the CISC processors instructions are not all long the same. The second part contain, in our example, the address of the memory location that we want to increment (0010 0100 1000, assuming that it uses 12 bits to address the memory).

Every instruction set is made in this way. The difference in the instruction set between a CISC and a RISC processor is that the latter uses an instruction set with a fixed instruction width.

The datasheet of a microprocessor can show you exactly how every instruction is made. If you want to see an example of how an instruction is made I advise you to start with old processors datasheet because they are less complex and are easier to understand. Take a look at the Z80 Datasheet, from page 101.

Coming to the question, essentially no. The CISC instruction does not contain the single microcoded instructions, but only a code that identifies the operation we want to do and the necessary data (value to load, address of the memory location...) to execute the instruction. The CPU has a decoder that when read the code knows what to do for that specific instruction and, if it's a microcoded instruction, it knows how to decompose it. As you can see the number of microcoded instructions in which an instruction is divided isn't depending on the lenght of the instruction and it's something "hidden" in the CPU itself, not accessible from the outside. The same goes for the opcode of the "micro" instructions.

This is a simplistic answer, but it tell you essentially how the things works. You can immediately see why the decoder of a CISC processor, particularly if it uses microcode, like the x86 CPUs, is much more complex than its counterpart RISC.