As far as I know, gating a clock in an FPGA is a very bad design practice because it can lead to clock skew and higher power consumption. This is specially true for the system's main clock, but what happens with slower devices such as SPI?
If the SPI clock signal is kept high at all times except when the device in question is going to send data, would it be acceptable to gate it? (ss | sck, to keep some of all the slaves except from 1 disabled).
I don't see how there could be a clock skew problem, given that this clock will be used only by one master and the enabled slave at each time.
Best Answer
If you look at any SPI device, they don't even expect or require a running clock. The clock might be even gated internally by SS. So SPI bus may tolerate a continuous clock and may be compatible with it, especially if SS is enabled at correct phase and with proper setup and hold timing.
Having just a clock for SPI bus is completely different thing compared to an FPGA clock signal.
For SPI, it's just one generic data pin among others, even if it is used for synchronous communication on the other SPI wires.
For FPGA, clock pins have special handling inside the FPGA with direct wiring and strong buffers for distributing the clock signal accurately to logic cells that need a sharp well defined clock to make all logic cells tick with the same clock.
So for an FPGA, the SPI clock would just be a generic data pin among other SPI data signals, either sampled or generated by using the FPGA clock.