J-K Flip Flop and Toggle

"What does it mean when a flip flop performs a function like SET, CLEAR, HOLD, or TOGGLE?"

first I'll like you to explain about latches.There is not much difference between latches and flipflop.Latches don't have clock input but flipflop have clock inputs.Here is a simple Set-Reset latch
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Explanation for SET:From the name,it suggests that,when you apply Logic HIGH to 'S'(Set),this sets the output Q to logic HIGH.The not(Q) will be it complement(logic LOW)
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Explanation for RESET:If you apply logic HIGH to 'R'(Reset),it makes the output Q to logic LOW,then not(Q) will be HIGH.(note that 'S' should be in logic LOW at that time).
Explanation for HOLD:If you apply Logic LOW to both input(S and R),The output doesn't change.I mean,it HOLDS the past output.
Explanation for TOGGLE:If you apply both pins with logic HIGH,it leads to indeterminate state for SR latch and it's the limitation of SR latch,so if you consider J-K flipflop,when you apply both J and K with Logic HIGH,it changes the output(ie. output HIGH goes to LOW and vice versa).This is called as TOGGLING.

"I start with a clock signal that goes into each flip flop. From there, I really have no clue how to trace what's going on."

Please note that,clock signal is to activate the latch circuit.A Latch with Clock pulse is called as Flipflop.Applying clock signal to activate a latch is called as Triggering.There are two types of triggering.One is edge triggering and the other is level triggering.

.In level triggering,The flipflop is ready to get the input throughout the Level of the clock continuous.In edge triggering,The flipflop will be ready to get input only when the edge of the clock is detected.Always edge triggering is preferred.

No, your circuit is still a edge-triggered circuit. The pairs NAND1+NAND2 and NAND3+NAND4 lock the state of D when the clock rises from to low to high. Changing D when the clock is high (after the rising edge) does not affect the output.

Let's start with Clk = 0, then is S=1 and R=1.

Now let D=0 during the rising edge of the clock:

• The output of NAND4 will be high.
• The output of NAND3 will be low, because S is still high, thus R=0 => Q=0.
• The output of NAND1 is low.
• The output of NAND2 is high, thus S is high, and R keeps low.

The output of NAND4 will be kept high until the clock is low again because the input connected to R is low regardless of any change on D (after the rising edge).

Please note that the functionality of this circuit relies on the propagation delay of the gates.