Level-triggered flip-flops in shift register

digital-logic

I am studying shift registers. My book mentions that level-triggered flip-flops cannot be used to make a serial-in serial-out shift register. What is the reason for this?

Best Answer

If you use level-triggered flip-flops (without a two-phase, non-overlapping clock) then all of the flip-flops will be transparent at the same time. The input to the first flip-flop will propagate all of the way to the output of the last flip-flop whenever the clock input is asserted.

By the way, I think it is better to call a level-sensitive storage element a "latch".