All you have to remember, is that current flows through a diode in the direction of the arrow.
In the case of the OR gate, if there is no potential (i.e. logic 0, or ground) on both inputs, no current will pass through either diode, and the pull-down resistor R\$_{L}\$ will keep the output at ground (logic 0).
If either of the inputs has a positive (logic 1) voltage on its input (In 1 or 2), then current will pass through the diode(s) and appear on the output Out, less the forward voltage of the diode (aka diode drop).
The AND gate looks more challenging because of the reversed diodes, but its not.
If either input (In 1 or In 2) is at ground potential (logic 0), then due to the higher potential on the anode side due to the positive voltage from resistor R\$_{L}\$, current will flow through the diode(s) and the voltage on the output Out will be equal to the forward voltage of the diode, 0.7v.
If both inputs to the AND gate are high (logic 1), then no current will pass through either diode, and the positive voltage through R\$_{L}\$ will appear on the output Out.
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As an aside, diode logic by itself is not very practical. As noted in the description of the OR gate for example, the voltage on the Out terminal when there is a logic high (1) on either of the inputs will be the voltage on the input minus a diode drop. This voltage drop cannot be recovered using just passive circuits, so this severely limits the number of gates that can be cascaded.
With diode logic, it is also difficult to build any gates other than AND and OR. NOT gates are not possible.
So enter DTL (diode transistor logic), which adds an NPN transistor to the output of the gates described above. This turns them into NAND and NOR gates, either of which can be used to create any other kind of logic function.
Sometimes a combination of diode logic and DTL will be used together; diode logic for its simplicity, and DTL to provide negation and regeneration of signal levels. The guidance computer for the Minuteman II missile, developed in the early 1960's, used a combination of diode logic and diode transistor logic contained in early integrated circuits made by Texas Instruments.
What you call an ":" is a divide symbol, NOT a ":".
Below Divide = "/". :
So /32 = divide by 32 = 5 stage counter.
Each stage divides by 2 in a binary counter (eg CD4040) so for 1 2 3 4 5 stages the divide ratio is 2 4 8 16 32.
/2 is a one stage counter = a flipflop configured to toggle when clocked.
The bottom lines do what the labels says = reset line.
The dividers are reset to 00000 and 0 respectively.
The box labelled "td" is explained in note 2 - it's a time delay - read the note.It's not complicated - it means EXACTLY what it says. ie there is a delay due to physical circuit parameters.
Best Answer
For CMOS logic parts like the 74HC family, the inputs are very high impedance, and don't assume any particular level when left unconnected. They must always be connected either directly, or through a resistor, to Ground or Vcc, in order for the chip to reliably see them as Low or High. ALL unused inputs MUST be connected to Vcc or Ground, even on the unused gates in the chip.
For bipolar TTL (plain 74xx, 74LS, 74ALS) the inputs source current, so will normally appear as high when not connected, and must be connected to Ground to be seen as a low.
As the comments mention, a bypass capacitor is desireable, but the lack of one wouldn't cause a problem with the simple test circuit you are using.