I am trying to find a controller chip for either SRAM or S/DRAM which can properly manage access of the memory from one or more devices (i.e. microprocessors). I have been up and down Google and all I have been able to find are academic discussions and silicon level IP. What I would like is an on the market IC which can accomplish this. Speed is not particularly important, I am mostly interested for curiosity/experimentation purposes, and less for practical aspects.
Multi-processor memory controller chips
memorysdramsram
Related Solutions
Memory cells are arranged in a matrix
This is a 16-bit memory, 1 bit wide, so it needs 4 address lines to address each individual bit. That's the a3..a0 lines at the left. a0 and a1 enter the green 2-to-4 demultiplexer. An N-input demultiplexer can have 2\$^N\$ output lines, and the binary input indicates which of those will be active. That's the row select.
The column select does something similar, but uses a multiplexer to select 1 of 2\$^N\$ lines as the output signal. So the combination of row select and column select can address an individual memory cell.
This is Random Access Memory because any bit is directly accessible, no matter what the address is. And it goes for DRAM as well as SRAM. SRAM needs more hardware to store a bit (4 or 6 FETs) than the DRAM shown, which needs only 1 FET per bit. The data is stored in the capacitors. Capacitors have leakage, and after some (very short!) time the data will be gone. That's why DRAM needs frequent refreshing: the data is continuously read and rewritten between accesses. This adds some extra hardware to the device, but a DRAM die is still much smaller than an SRAM die with the same capacity.
From the outside, each memory chip is organized as 1M words of 1 bit each, which means that it takes 20 address bits to specify a word.
Internally, the memory is physically organized as a square matrix of 1024 rows and 1024 columns, with one bit in each position in the matrix.
There are at least two reasons that the physical organization is important to the question:
The memory chip only has 10 address pins. The full 20-bit address is fed into the chip in two stages, the 10-bit row address first, and then the 10-bit column address.
When a refresh operation occurs, an entire row is refreshed all at once.
Best Answer
I think what you have in mind might be a "DMA controller". DMA = "Direct Memory Access". The microprocessors will need to be DMA-compatible.
An alternative would be to use bidirectional buffers for this particular memory bank, one set per microprocessor, and some sort of "shared memory bank active" semaphore or handshake between microprocessors such that no two are trying to access the same memory at the same time (a condition that could have all sorts of bizarre side effects); shared memory access isn't super-simple to implement, and timing for controlling that semaphore would be critical.
The low-tech way of accomplishing it would be to equip each microprocessor with a slot for SD cards (of whichever footprint). Then you could "sneakernet" the shared memory.