In a logic circuit, I have an 8-bit data vector that is fed into an ECC IC which I am supposed to develop the logic for and that contains a vector of 5 Parity Bits. My first step to develop the logic (with logic gates, XOR), is to figure out which parity bit is going to check for which Data bits (since they are interlaced). I am using even parity, and following general hamming code rules (a parity bit in every 2^n ), I get the following sequence of output:
P1 P2 D1 P3 D2 D3 D4 P4 D5 D6 D7 D8 P5
Following the General Hamming Algorithm:
For each parity bit, Position 1,2,4,8,16 and so on… (Powers of 2), we skip for the first position n (n-1) and we check 1 bit, then we skip another one, the check another one, etc… we repeat the same process for the other bits, but this time checking/skipping every 2^n, where n is the position they occupy in the output array (P1 P2 D1 P3 D2 D3 D4 P4 D5 D6 D7 D8 P5)
Following that convention, I get:
P1 Checks data bits -> XOR(3 5 7 9 10 12)
P2 Checks data bits -> XOR(3 6 7 10 11)
P3 Checks data bits -> XOR(5 6 10 11 12)
P4 Checks data bits -> XOR(9 10 11)
Am I right? The thing that confuses me is that if I should start checking counting the parity bit as one of the 2^n bits that are supposed to be checked, or 1 bit after that specific parity bit. Pretty much sums up to if it is inclusive or not.
Thank you for your help in advance!
Cheers!
Best Answer
It is done inclusively ie by undertaking the parity bit under consideration, they are designed in such a way that along with the parity bit itself the data word or message bit generates the desired parity type in your case even parity.
Look at the image from wikipedia
Only parity 1 is included while calculating at position one and so on.
Remember don't confuse between position and parity number, the bit-stream are numbered (1-n), where n is the size of codeword.
Hence your P1 is position 1,your P2 is position 2, P3 is position 4, and P4 is position 8.