PCB thermal via design for qfn package

That's going to be determined by the thickness of the stencil and the opening size, or if no stencil the thickness of the solder paste printed on the board. I believe it's a warning that too much paste will float the part and then you might not get good joints all around, or maybe the part might be uneven etc.

The only way you could affect it is if you are defining the paste layer yourself then you define the opening and put an assembly note in about stencil thickness.

But really I would say you should leave this to your assembly house to adjust correctly for their process when they order the stencils. They have to look at all the parts in the board and find a method that will work for all of them, it's part of the magic of being a good assembly house.

Here by the way is a link that talks about it more. Note that their guideline if a 2-3 mil standoff is "after assembly". Not a you should have a 2-3 mil standoff before assembly...

I would not go with this. Small designs will not necessarily heat up that much, but running an exposes pad so close to your traces is risky. Depending on volume, you will get some boards where part of that trace is exposed, or the via mask is scraped off. The wear and tear on the board depending on use case might expose something, or maybe that part does heat up a slight amount and over time causes unexpected behavior.

Overall it is just not good design practice. Use another layer.