Power consumption of a FPGA

This is an interesting question. From personal experience, I have left FPGAs powered up for hours in an unprogrammed state while performing checks on the rest of the circuitry when a new board comes in from the assembly house. I have not noticed any detrimental effects from doing so. But I've honestly never thought about it.

I looked around to try and find a recommendation from an FPGA manufacturer but could not find one. The only statement I found regarding this state is from a Lattice whitepaper and regards the design of the FPGA itself and not how it should be used:

Pre-Programmed Static Quiescent Device Power Consumption is the amount of power consumed by the FPGA prior to the device being programmed. For quiescent device power consumption the FPGA is in a non-programmed state, yet has been powered. It is important that the device not consume significant power during this time, as conceptually the FPGA device could draw excessive power and potentially shut down power supplies, preventing the board from successfully initializing itself and the system.
The FPGA supplier therefore has to carefully design transistors that have a low static 3 Designing for Low Power A Lattice Semiconductor White Paper power footprint, without compromising in areas where higher performance is required (e.g. I/O and SERDES)

Xilinx likewise mentions what the quiescent current is so that you can design your power supply accordingly. But does not mention what the effect on the device is of leaving it in such a state:

Static or quiescent power is mainly dominated by transistor leakage current. When this current is listed in data sheets, it is listed as ICCINTQ and is the current drawn through the VCCINT supply powering the FPGA core.

I would be very interested to hear if anyone has experienced damage to a device from leaving it in a quiescent state. But I think as long as the power supply is properly matched to the device, there should be no problem.

The reason they direct you to a power estimation tool is because the power consumed depends very heavily on how hard the device is working.

Intel know that their processors will be clocked at the max rated frequency (at least some of the time) and that all the processing units will be used (at least some of the time).

Xilinx have no idea what their customers will do. It may be that the design is slightly too big for a small device, so needs the larger device, hence only (for example) 60% of it is used and the other 40% lies idle, not consuming dynamic power. Most time customers cannot clock the entire device at anything close to the theoretical fmax, so that reduces dyanamic power also.

If you were to calculate a theoretical max power dissipation, it wouldn't help much as you'd then end up overspecifying your power and cooling subsystems by a factor of (guessing) 2x to 4x!