Question on dsPIC33F PWM Period and Duty Cycle Calculation

You should check out example 7-2 in the pic24E family reference manual (FRM) titled "Code Example for Using PLL with 7.37 MHz Internal FRC":

// Select Internal FRC at POR
_FOSCSEL(FNOSC_FRC & IESO_OFF);
// Enable Clock Switching and Configure Primary Oscillator in XT mode
_FOSC(FCKSM_CSECMD & OSCIOFNC_OFF & POSCMD_NONE);

int main()
{
    // Configure PLL prescaler, PLL postscaler, PLL divisor
    PLLFBD=63;            // M=65
    CLKDIVbits.PLLPOST=0; // N2=2
    CLKDIVbits.PLLPRE=0;  // N1=2

    // Initiate Clock Switch to FRC oscillator with PLL (NOSC=0b001)
    __builtin_write_OSCCONH(0x01);
    __builtin_write_OSCCONL(OSCCON | 0x01);

    // Wait for Clock switch to occur
    while (OSCCONbits.COSC!= 0b001);

    // Wait for PLL to lock
    while (OSCCONbits.LOCK!= 1);
}

It looks like the critical step you're missing is __builtin_write_OSCCONL(OSCCON | 0x01);

Also, looking at the math: 7.37*(76/(2*2)) == 140.03MHz which is slightly outside the allowed range, assuming that 140MHz is actually the maximum range (don't ask me why but for some reason it seems like it may be 120MHz).

If this still doesn't work then perhaps there's just an issue with your power supply. The internal FRC oscillator is unstable under temperature and voltage stress, so perhaps you should check to see if you have too much noise. This would make the FRC wonky as well as the VCO used in the PLL, preventing a lock.

If you look at table 30-18 in the pic24EP128MC206 datasheet, it tells you that over the temperature and voltage range you have about a ±1% for some models and ±2% for others. Figure 31-9 shows the variation with a stable voltage over a temperature range. There doesn't appear to be an analysis of voltage variation at a stable temperature.

If you're trying to get a stable run at a high frequency I would just grab a crystal.

EDIT (from comment): So from the sounds of your other posts about your conditions it sounds like you should look elsewhere for a problem. What's the frequency of the ripple? Did you size the internal Vreg capacitor properly? It sounds like since this is a locking issue and not a setting issue you're having some other problems with the board that aren't related to your code.

EDIT:

Glad this turned out to be the right answer! Good luck debugging the rest of the board!

On the bottom of page 350 of the microcontroller datasheet, it mentions that writing a small value to the timer value register during the overflow interrupt might cause the next interrupt to be triggered only on the next pwm iteration, since the timer continues to count while the interrupt routine is being executed.

An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written.

This is confirmed by the fact that the pwm value is held high for one entire pwm clock period + what looks like the timer length (based on the surrounding lengths). The value being written to the timer length register is probably close to 0 at the time of error, so it is quite viable that the counter has passed the smaller value during the interrupt, and would only trigger on the following cycle.

This could be fixed by increasing the sinusoid minimum level to a level higher than the time it takes to execute the ISR, or changing the mechanism by which the new level is set. The top of page 351 details how this may be done.