Realisation of asynchronous decade counter

counterdigital-logic

Here is the illustration of the counter:
enter image description here

Can you please explain in detal what happens here? Why are J and K inputs always 1 and how does CLR reset these flip-flops?

Best Answer

An asynchronous counter means that the states of flip flops dont change simultaneously. This is evident by the fact that all flip flops are clocked by different clocks rather than a single master clock.

As far as working is concerned, a timing diagram may help :

enter image description here

1) First flip flop (Q0) changes state on PGT of the clock.

2) Second flip flop changes state on the PGT of its clock. Since it is clocked by Q0, it will change states when corresponding transition occurs for Q0 rather that Clock.

....and so on for subsequent flip flops.

Why are J and K inputs always 1 ?

The flip flops need to toggle on the occurance of PGT. Since a J-K flip flop toggles only when both inputs are HIGH or 1 ( also called toggle mode of operation), hence they must be kept high.

How does CLR reset these flip-flops ?

If you look carefully at 'your' circuit, the input of the Nand gate is connected to the 2nd and 4th flip flops. The output of Nand gate is low only when both the inputs are HIGH. Plus you have active Low reset. So whenever the 2nd and 4th flip flops go HIGH for the first time simultaneously, which happens for binary 1010 or decimal 10, the flip flops will all reset and recycle to initial state ie 0000. Typically this is used to create counters which count less than the maximum no of available states. In your case, 4 flip flops should have counted till 1111 or decimal 15. However, presence of Nand terminates the count early.

Related Solutions

3 bit synchronous counter design d flip flop

The key thing is to treat each bit individually.

For example, for the low-order bit, lets call it next_state[0].

state     | next_state[0]
---------------
   000    | 0
   001    | 0
   010    | 1
   011    | X
   100    | 0
   101    | 0
   110    | 0
   111    | 1

So you can write

next_state[0] = state[0] & state[1] & state[2] | ~state[0] & state[1] & ~state[2]

If you are building this with discrete logic you could simplify this to

next_state[0] = state[1] & (state[0] & state[2] | ~state[0] & ~state[2])

And you have an equation you can use to drive the flip-flop that will generate the next condition for the low-bit of the state variable.

Finding the equations for the other two state bits works the same way.

Electronic – In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth

The circuit you cited is a ripple counter, not a synchronous counter. It actually has eleven states, 0000 through 1010, but as soon as the last state is reached, the NAND gate immediately (asychronously) resets the flip-flops to the 0000 state.

In a synchronous counter, all of the flip-flops would share a common clock, and you'd control the sequence of states by driving their J and K inputs. This would require a few additional gates, which would include decoding the 1001 state so that the counter goes directly to the 0000 state on the next clock edge.

Best Answer

Related Solutions

3 bit synchronous counter design d flip flop

Electronic – In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth

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