3 bit synchronous counter design d flip flop

counterflipflop

Any idea how I would go about designing a 3 bit synchronous counter in regards to having the following states 

111->001->110->101->100->000->010->111

I drew up a present state and next state table etc… not really sure where to go from here, I have designed in logism a start schematic with a CLK, CLR and PRE, with 3 D type Flip flops as these are the ones I am required to use, but I am unsure where to go from here.

Best Answer

The key thing is to treat each bit individually.

For example, for the low-order bit, lets call it next_state[0].

state     | next_state[0]
---------------
   000    | 0
   001    | 0
   010    | 1
   011    | X
   100    | 0
   101    | 0
   110    | 0
   111    | 1

So you can write

next_state[0] = state[0] & state[1] & state[2] | ~state[0] & state[1] & ~state[2]

If you are building this with discrete logic you could simplify this to

next_state[0] = state[1] & (state[0] & state[2] | ~state[0] & ~state[2])

And you have an equation you can use to drive the flip-flop that will generate the next condition for the low-bit of the state variable.

Finding the equations for the other two state bits works the same way.

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