Electronic – Designing a synchronous counter with d flip flops

counterdigital-logicflipflop

I have to design a counter with two inputs: x and y. If y = 0, the counter behaves like a 3-bit ring counter, and if y = 1, it behaves as a 3-bit Johnson counter. If x = 0, it counts up, and if x = 1, it counts down. I may only use D flip flops, and any logic gates I require.

For reference, here are the state tables of a 3-bit ring and Johnson counter (in that order):

Ring table

Johnson table

So naturally, I created this big table of states:

Table of states

Since there are two inputs, and three states, each following state depends on five bits. Therefor the K-maps for Q1+, Q2+ and Q3+ (which are actually D1, D2 and D3 for the flip flops) are maps of five variables, making this somewhat complicated.

The question is: is there a way to do the minimization with k-maps in a simpler manner (perhaps I am missing something)? Or, if there is no way to simplify the minimization, then is it wiser to use k-maps of five variables or perhaps another method (quine-mccluskey maybe, or something completely different)?

Best Answer

A design simplification is to first design the up/down Johnson and ring counters independently. Then just place a mux that selects Q* of either one depending on y.

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Related Solutions

Electronic – How to implement a simple finite state machine with 2 T flip-flops

This looks like a homework question, which I won't answer. But here are some pointers:

You cannot represent more states than what you have available -> that means that you will have to go to the next higher state (i.e. 2 FF's for 4 states) or use only one FF per state. (i.e. FF #1 correlates directly to A).
option #1 ( 2 FF's and 4 states) is more economical but you have to make sure that the unused state does n't not get activated and then locks out.
- you might draw this as a 4th state "D" with loops back to itself.
- what is generally considered safe design is that you always have explicit transitions AWAY from the unused state in case it gets activated.
option #2 uses more FF's but cannot have any hidden states.
- it is inherently safer.
- it is known as a "one hot" design and thermometer codes are examples of this.

Your choice of states "A = 00" etc. will make the design simpler or more complicated. SO may want to go with what you decribe or you may want to go with state C = "10". You should look at all possibilities.

The first SM, only uses 0 or 1 as an input because it only has one input variable. They should have used a variable for clarity anyways. You'll notice in the table that it is marked as "x" but not in the diagram.

3 bit synchronous counter design d flip flop

The key thing is to treat each bit individually.

For example, for the low-order bit, lets call it next_state[0].

state     | next_state[0]
---------------
   000    | 0
   001    | 0
   010    | 1
   011    | X
   100    | 0
   101    | 0
   110    | 0
   111    | 1

So you can write

next_state[0] = state[0] & state[1] & state[2] | ~state[0] & state[1] & ~state[2]

If you are building this with discrete logic you could simplify this to

next_state[0] = state[1] & (state[0] & state[2] | ~state[0] & ~state[2])

And you have an equation you can use to drive the flip-flop that will generate the next condition for the low-bit of the state variable.

Finding the equations for the other two state bits works the same way.

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