PCB Design – Should Extra Unused Copper Be Removed from a Power Plane in 4 Layer PCB?

altiumpcb-designvia

I am designing 4 layer PCB which has the following stack up structure:

  • Layer 1 (top layer) signal
  • Layer 2 (inner layer 1) power plane
  • Layer 3 (inner layer 2) ground plane
  • Layer 4 (bottom layer) signal (consists of an RF antenna track)

I have connected all the 5V and 3.8V connections from top/bottom layer to power plane through the through hole vias.
As per the layer stack up, power plane and ground plane both are adjacent to each other and dielectric thickness is 1mm.

  1. Will this create capacitance between PWR and GND planes? Will it create any problems?
  2. Should I remove extra copper from the power plane?
  3. As I have used through hole vias instead of blind vias, there are unused vias (via stubs) in PCB. Can these floating vias cause any problems with the PCB?

Best Answer

  1. Yes, it adds capacitance between power planes. Two conductors separated by an insulator is a capacitor. It will not create any problems, on the contrary, it is a very much desired property to have distributed capacitance between power planes.

  2. Based on 1), definitely not.

  3. It depends what signals will pass through the vias and will the stubs of a via be harmful. For RF and high speed data signals, maybe, for low frequency stuff, unlikely.

Related Topic