What do you mean by negative setup and hold time i.e what happens if hold time is negative or setup time is negative. Does -ve setup or hold have any advantage ?
Significance of negative setup and hold time
-setupflipflop
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You're forgetting a couple of important facts:
- A flip-flop isn't a single atomic gate, but made up of multiple gates.
- It takes time for a signal to pass through a gate (or propagate).
- There is no such thing as a pure square wave.
Take this diagram of a transparent latch:
Assume each gate requires one "time unit" to propagate the signal.
The D signal arrives at the input to one NAND gate at \$T_0\$. It also arrives at the NOT gate at \$T_0\$. It then leaves the NOT gate and arrives at the second (lower) NAND gate at \$T_1\$. So the shortest time before the CLK signal can have any effect on the input NAND gates will be \$T_1\$ since that is when the D signal has propagated to them. SO then the output of those NAND gates will be propagated as stable at \$T_1\$ for the upper one, and \$T_2\$ for the lower one. Then it's on to the next two NAND gates. Those again add 1 time unit to each of the signals. On top of that, the outputs of those then feed back into each other's inputs, so as they change they propagate a new signal through themselves, each adding another time unit.
Only when the outputs have stopped sorting themselves out will the gate be "stable", and that is when it's in the "hold" state. It could be many time units.
Then of course you have the "square" wave, which is far from square. Each change from low-to-high or high-to-low takes time. Only once a signal passes a certain threshold will it be seen as either high or low. Different factors affect how long those transitions take, including the gate capacitance of the MOSFETs in the logic gate, the actual switching time of the MOSFETs, etc.
So you can see there is a certain amount of time taken for a flip-flop to change from one state to another, and at different points during that time different things happen with the gate.
You mention Altera so I assume this is an FPGA design.
If this really is the ideal case (you're ignoring the wire delays due to physical location of the elements) then yes, ideal tCOmin is 3ns. This is the best case (shortest delay, fastest clock) under ideal conditions.
However, post-synthesis simulation will reveal a more meaningful result once the circuit elements have been mapped to specific flip-flops at specific locations on the FPGA. This constrains the available wiring routes, which is where the wiring propagation delay is determined. For a large FPGA chip with high utilization, it becomes more likey that placement is not ideal. Since the worst (longest) tCOmin total delay is what constrains how fast the system can be clocked, the synthesis tools analyze the whole FPGA system and report on whichever circuit has the worst tCOmin, so that the designer can focus their efforts to make a large system perform as required.
Best Answer
Setup times and hold times describe the limits relative to the active clock edge of a "window" within which the input data must be valid for the data to be reliably recognized. The diagram below (you can ignore the bottom Q output part) shows the situation for assumed positive hold and setup times, but you can imagine them negative.
If setup time is negative, then the absolute latest that the data can become valid is actually after the active clock edge, Obviously the hold time must be positive and of greater magnitude or there would be no window for data validity.
If the hold time is negative, then the absolute earliest the data no longer needs to be valid is before the active clock edge, so it can change just before the clock edge and the previous value will be correctly recognized. Obviously, the setup time must be positive and of greater magnitude or there would be no window.
As to possible advantages- think about the situation where you are trying to increase clock frequency as much as possible.