Simple 1 bit register

I am trying to write a 1 bit shift register with this code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity simple_one_bit_serial_shift_register is
   port(
      clk      : in  std_logic;
      reset      : in  std_logic;
      shiftin : in std_logic;
      shiftout : out std_logic_vector(1 downto 0)
      );

end simple_one_bit_serial_shift_register;

architecture simple_one_bit_serial_shift_register_behavior of simple_one_bit_serial_shift_register is 

    signal shiftreg : std_logic_vector(31 downto 0);   

begin
process (clk,reset) 
    begin  
        if rising_edge(clk) then
            shiftreg <= shiftreg(30 downto 0) & shiftin;
        end if;    
end process;
shiftout <= shiftreg(31);
end simple_one_bit_serial_shift_register_behavior;

but when simulating I get the errors

ERROR: [VRFC 10-925] indexed name is not a std_logic_vector [C:/Users/Darren/Desktop/project_6_1_3/project_6_1_3.srcs/sources_1/new/1Bit_delay_register.vhd:28]

but they both are vectors and I cant seem to find much on this problem

Edit : Testbench

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Entity one_bit_shift_tb is
end one_bit_shift_tb;

architecture behaviour of one_bit_shift_tb is
    component simple_one_bit_serial_shift_register
   port(
          clk      : in  std_logic;
          shiftin : in std_logic;
          shiftout : out std_logic
          );
    end component;


    signal clk: STD_LOGIC;
    signal shiftreg : std_logic_vector(31 downto 0);
    signal shiftin : std_logic;
    signal shiftout : std_logic;

begin
    u_shifter: simple_one_bit_serial_shift_register 
    port map (clk =>clk, shiftin => shiftin, shiftout => shiftout);    
    process
    begin
        clk <='0';
        wait for 5 ns;
        clk <='1';
        wait for 5 ns;
    end process;    
    process    
    begin             
        shiftin <='0';
        wait for 50 ns;
        shiftin <='1';
        wait for 50 ns;
        shiftin <='0';
        wait for 50 ns;
        shiftin <= '1';
        wait;
    end process;
end behaviour;