Was an ASIC Design Verification Engineer at Qualcomm. In the most simple way I can explain it:
Testing: Making sure a product works, after you've created the product (think QA).
Verification: Making sure a product works BEFORE you've created it.
They're both testing, just that verification is more complicated because you have to figure out a way to test the product before it exists and you have to be able to make sure it works as designed and to spec when it actually comes out.
For example, Intel is designing their next processor, they have the specs, they have the schematics and the simulations. They spend $1 Billion USD to go through fabrication and manufacturing. Then the chip comes back and they test it and find out that it doesn't work. They just threw a lot of money out the window.
Throw verification in. Verification engineers create models that simulate the behaviour of the chip, they create the testbench that will test those particular models. They get the results of these models and then they compare it with the RTL (model of the circuit writting in a hardware design language) results. If they match, things are (usually) OK.
There are a number of different methodologies for the verification process, a popular one is Universal Verification Methodology (UVM).
There is a lot of depth in the field and people can spend their entire career in it.
Another random tidbit of information: Usually you need 3 verification engineers for 1 design engineer. That's what everyone in the field says anyway.
EDIT: A lot of people think of verification as a testing role, but it's not; it's a design role in itself because you have to understand all the intricacies of your IC like a designer does, and then you have to know how to design models, testbenches, and all the test cases that will cover all the feature functionality of your IC, as well as trying to hit every single line of RTL code for all possible bit combinations. Remember that a processor nowadays has billions of transistors due to the fabrication process allowing smaller and smaller (now 14nm).
Also, in large corporations like Intel, AMD, Qualcomm, etc, designers don't actually design the chip. Usually the architect will define all the specs, layout the types of pieces that need to go together to get a particular function with a specific requirement (i.e. speed, resolution, etc.), and then the designer will code that into RTL. It's by no means an easy job, it's just not as much designing as a lot of engineers coming out of school think it is. What everyone wants to be is an architect, but it takes a lot of education and experience to get to that point. A lot of architects have PhD's, and like 15-20 years of experience in the field as a designer. These are brilliant people (and sometimes crazy) who deserve to be doing what they're doing, and they're good at it. The architect on the very first chip I worked on was a bit awkward and didn't really follow some social norms, but he could solve anything you're stuck with regarding the chip, and sometimes he would solve it in his head and tell you to look at one signal and you'd be like, "how the hell did he do that?". Then you ask him to explain and he does and it goes way over your head. Actually inspired me to read textbooks even though I've graduated already.
Basically a specification is a list of requirements. A requirement is generally defined as any statement that has the word "shall" in it. For example, a specification for a digital multimeter might include the following requirement: " The DMM shall have a display resolution of 3000 counts".
A function is a capability of the equipment. Again, using A DMM as an example, a function would be the ability to measure AC volts. A feature is a particular capability that makes the device stand out. For example, the DMM features a wide bandwidth of 100 kHz with the AC volts function, which is better than most DMMs.
Features and functions both must be specified in the requirements or they won't be designed into the device.
Configuration refers to whether the device as designed will meet all of its specifications. Again, for example, if the device uses 5% resistors, it would be hard to verify that is meets an accuracy requirement of 1%.
Best Answer
The answer I've got (thanks to user3467290) :
There is a very important difference between these forms.
In the first, the register value will be generated, using all defined constraints, + the constraint you wrote in this action (field1 == 1). The new generated value will be written to the DUT.
In the second code, what you state is that you want to modify only one field of the register - field1. What will happen is that vr_ad will get the current value of the register from the e model (the shadow model), change field1 - and will write the new value the the register in the DUT. None of the other register's fields will be changed. Also - there is no check that the value you assign to field1 complies with the constraints defined on this register.